Suggestion: run riscv-tests (rv32im etc)

[stskeeps]

Quite a few tests here that really get around: https://github.com/riscv-software-src/riscv-tests/tree/master/isa/rv32ui

[chriseth]

Thanks for the link! They look a bit difficult to compile, but they probably cover some important edge-cases!

[stskeeps]

They're actually not so terribly bad, did it for a RISC-V to EVM transpiler attempt, see riscv_tests.h for how to set up the surrounding environment, then it's just a clang or gcc configured to target rv32i; https://github.com/YosysHQ/picorv32/tree/master/tests uses less Makefile magic

[lvella]

An update where we stand on this issue: we aim to be able to run every rv32u{i,m,a} tests that makes sense for us, and we do it for all instructions we currently support (see issue #438). But there are some that I don't think it makes sense for us, there is an write-up about it in riscv/tests/instruction_tests/README.md.

That said, our assembler does not support numbered labels of the kind:

1:
    j 1f
2:
    j 1b
1:
    j 2b

so we had to manually replace these labels with absolute text labels.

[leonardoalt]

I think we have enough instructions tests now and can close the issue.