generator_bootcamp的紀錄

[poweihuang17]

2.5 從IPXACT Example後面都沒法使用。因為沒有DSP那個檔案。

[poweihuang17]

需要學習IPXACT, AXI4-stream, AXI4-lite等技術。

[poweihuang17]

FIR Filter Generator這個也是很有趣。想把這個code看懂。 class MyManyDynamicElementVecFir(length: Int) extends Module { val io = IO(new Bundle { val in = Input(UInt(8.W)) val valid = Input(Bool()) val out = Output(UInt(8.W)) val consts = Input(Vec(length, UInt(8.W))) })

// Such concision! You'll learn what all this means later. val taps = Seq(io.in) ++ Seq.fill(io.consts.length - 1)(RegInit(0.U(8.W))) taps.zip(taps.tail).foreach { case (a, b) => when (io.valid) { b := a } }

io.out := taps.zip(io.consts).map { case (a, b) => a * b }.reduce( + ) }

[poweihuang17]

感覺它這樣整合的技術非常厲害，應該學學。就像那個DSP utils，還有henry cook 那個memory mapped, lazy generation，還有generator，這真的是趨勢。還可以控制length來產生FIR filter，真的很強。

[poweihuang17]

craft_BlindModule_edu.berkeley.cs_1.0.xml 這個檔案產生不了，不然真想好好研究一下產生IPXACT。像是這個： Port mappings Interfaces Memory maps Generator parameters

[poweihuang17]

只能先跳過2.5，前往3.1了。

[poweihuang17]

3.1感覺要教parameters，不過要等煮完菜飯後再弄了。希望今天可以把3完全弄完。

[poweihuang17]

3.1的問題：實在不知道為什麼scala沒有辦法抓出三種sequence。

Example: Type Matching and Erasure Type matching has some limitations. Because Scala runs on the JVM, and the JVM does not maintain polymorphic types, you cannot match on them at runtime (because they are all erased). Note that the following example always matches the first case statement, because the [String], [Int], and [Double] polymorphic types are erased, and the case statements are actually matching on just a Seq.

val sequence = Seq(Seq("a"), Seq(1), Seq(0.0))

sequence.foreach { x =>

x match {

case s: Seq[String] => println(s"$x is a String")

case s: Seq[Int]    => println(s"$x is an Int")

case s: Seq[Double] => println(s"$x is a Double")

}

}

List(a) is a String List(1) is a String List(0.0) is a String

sequence: Seq[Seq[Any]] = List(List(a), List(1), List(0.0))

Note that Scala compilers will usually give a warning if you implement code like the example above.

[poweihuang17]

是不是因為被當成Sequence[Any]呢？

[poweihuang17]

下面的這個敘述也是有點奇怪。

IOs with Optional Fields

Sometimes we want IOs to be optionally included or excluded. Maybe there's some internal state that's nice to be able to look at for debugging, but you want to hide it when the generator is being used in a system. Maybe your generator has some inputs that don't need to be connected in every situation because there is a sensible default.

[poweihuang17]

3.1的這段也不太懂： sealed trait Verbosity implicit case object Silent extends Verbosity case object Verbose extends Verbosity

[poweihuang17]

extends verbosity這樣的trait也可以當作implicit type喔？

[poweihuang17]

3.2 裡面的這段看不太懂： Things to watch out for

(I.e., things that we actually screwed up while writing this.)

Getting the step in the right place. Software and hardware execute differently; it's easy to get this wrong.
This test is weak because it is very sensitive to how the IOs and registers are sized. Implementing a software golden model that observes wrapping behavior at arbitrary data bit widths can be complicated. Here we just make sure that we only pass in values that fit.

[poweihuang17]

3.2 最後介紹了一個Vec，看起來這是一個專門針對chisel的collection。 這段code感覺蠻重要的。 Hardware Collections

Example: Add run-time configurable taps to our FIR The following code adds an additional consts vector to the IO of our FIR generator which allows the coefficients to be changed externally after circuit generation. This is done with the Chisel collection type Vec. Vec supports many of the scala collection methods but it can only contain Chisel hardware elements. Vec should only be used in situations where ordinary Scala collections won't work. Basically this is in one of two situations.

You need a collection of elements in a Bundle, typically a Bundle that will be used as IO.
You need to access the collection via an index that is part of the hardware (think Register File).

class MyManyDynamicElementVecFir(length: Int) extends Module {

val io = IO(new Bundle {

val in = Input(UInt(8.W))

val out = Output(UInt(8.W))

val consts = Input(Vec(length, UInt(8.W)))

})

​

// Reference solution

val regs = RegInit(Vec.fill(length - 1)(0.U(8.W)))

for(i <- 0 until length - 1) {

  if(i == 0) regs(i) := io.in

  else       regs(i) := regs(i - 1)

}

val muls = Wire(Vec(length, UInt(8.W)))

for(i <- 0 until length) {

  if(i == 0) muls(i) := io.in * io.consts(i)

  else       muls(i) := regs(i - 1) * io.consts(i)

}

​

val scan = Wire(Vec(length, UInt(8.W)))

for(i <- 0 until length) {

  if(i == 0) scan(i) := muls(i)

  else scan(i) := muls(i) + scan(i - 1)

}

​

io.out := scan(length - 1)

}

[poweihuang17]

不過這段，我又有點不懂了。為什麼要突然用一個bithack呢？ class RegisterFile(readPorts: Int) extends Module { require(readPorts >= 0) val io = IO(new Bundle { val wen = Input(Bool()) val waddr = Input(UInt(5.W)) val wdata = Input(UInt(32.W)) val raddr = Input(Vec(readPorts, UInt(5.W))) val rdata = Output(Vec(readPorts, UInt(32.W))) })

// A Register of a vector of UInts
// fromBits(0.U) is a bit of a hack to have reg reset to zero
val reg = RegInit( Vec(32, UInt(32.W)).fromBits(0.U) )

}

[poweihuang17]

3.2 Interlude中有個我有點不懂：and valid should only be dependent on whether the source has data. Only after the transaction (on the next clock cycle) should the values update. 這段在講啥

[poweihuang17]

3.2 Interlude 中 還有一個問題，到底什麼是flipped，在stackoverflow上問了：Driver(() => new Module { // Example circuit using a Queue val io = IO(new Bundle { val in = Flipped(Decoupled(UInt(8.W))) val out = Decoupled(UInt(8.W)) })

[poweihuang17]

看到3.2的感想是，chisel 在STL這邊真厲害，像是DecoupledIO, Queues, Arbiters, Misc Function Blocks等，真的都是很重要的。