flo-dup
commented
2 years ago A way to solve that would be to dismiss the fictitious switches at the bus bar (A1 and A2 here). I've seen that on a specific single line diagram viewer, but I don't approve this approach as this does not really reflect the network graph.
A better solution suggested by @BenoitJeanson would be to see the other side of A1 and A2 (the side not connected to the busbar) as fictitious bus nodes. Then they should not be drawn as bus bar though.
Do you want to request a feature or report a bug? Bug
What is the current behavior? Cell detection cannot process some diagrams, leading to a diagram with all nodes with same abscissa
If the current behavior is a bug, please provide the steps to reproduce and if possible a minimal demo of the problem Create a voltage level reflecting following diagram and try to generate the single line diagram:
The resulting diagram has overlapping nodes:
What is the expected behavior? A readable diagram with nodes and wires not overlapping
What is the motivation / use case for changing the behavior? A readable diagram