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pranjalchanda08 / slash-sim

Slash Sim is a simple C based RV32 Instruction set simulator. This can be used to simulate any binary file that is compiled using RISCV toolchain.
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Test RV32 base instruction and behavior verification #11

Closed shibcreate closed 2 weeks ago

shibcreate commented 1 month ago

After validation of all RV32I instructions

pranjalchanda08 commented 1 month ago

@shibcreate,

Please use this branch to work on this task:

git fetch origin
git checkout 11-add-m-support-for-rv32im
shibcreate commented 1 month ago

Will do

pranjalchanda08 commented 1 month ago

Hi @shibcreate, I have renamed ur branch please sync to that

shibcreate commented 4 weeks ago

Okay 👍