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prasadp4009 / tbengy

Python Tool for UVM Testbench Generation
MIT License
49 stars 13 forks source link

Consider using open source FPGA tooling #2

Open mithro opened 2 years ago

mithro commented 2 years ago

It would be great to support the open source FPGA tooling from https://f4pga.org/ project. Examples on how to use the tooling for Xilinx 7 series parts can be found here -> https://f4pga-examples.readthedocs.io/en/latest/building-examples.html#xilinx-7-series

There are prebuilt binaries distributed through conda available at https://github.com/hdl/conda-hdl including SystemVerilog support using the Surelog->UHDM->Yosys tooling.

FYI - Xilinx has also published an open source version of the UniSim library @ https://github.com/Xilinx/XilinxUnisimLibrary

prasadp4009 commented 2 years ago

Hi @mithro , Thank you for bringing this up, I will plan this feature to perform synthesis and bitstream generation for Xilinx as well as other FPGAs supported by f4pga in my next release.