Open prasimix opened 5 years ago
ULX3S just has 25 MHz onboard and it can take 10 MHz as well. It should work although it will be at its lower edge of acceptance, external input clock freq according to datasheet can be from 10-400 MHz
On 7/28/19, prasimix notifications@github.com wrote:
@emard, we've discussed about need of master/reference clock for peripheral modules if they have FPGAs deployed since it could be more cost efficient and accurate to introduce master clock on the new master ("CPU") board then to use separate oscillators on each modules and take extra care about inter-module sync. Question is what clock frequency to use (e.g. VXI is using 10 MHz, but ULX3S use 25 MHz) and what price/accuracy class?
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I don't see a problem with using 25 MHz (or even 50 MHz?) as master clock (e.g. that could be also beneficial at least for Ethernet :). Why we should follow VXI spec which is defined some times ago? Another thing is if we want to deploy a very accurate reference that is easier (and cheaper) to find something on 10 MHz then 25 or 50 MHz.
well I'd prefer having e.g. oven stabilized oscillator on board and placeholder for rubidium clock reference if space permits something small like PRS10 it outputs 10MHz sinewave. To measureme any physical, value it technically ends up measuring the time :)
https://www.thinksrs.com/products/prs10.html
On 7/29/19, prasimix notifications@github.com wrote:
I don't see a problem with using 25 MHz (or even 50 MHz?) as master clock (e.g. that could be also beneficial at least for Ethernet :). Why we should follow VXI spec which is defined some times ago? Another thing is if we want to deploy a very accurate reference that is easier (and cheaper) to find something on 10 MHz then 25 or 50 MHz.
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Huh, for $1500 that must be a real stuff! It is also significant that it provides 10 MHz. I do believe that we can start to think of it in foreseeable future, but for the beginning I think that will be much easier to make a whole think attractive with something below $100. I'll try to find something in that price range (and obviously with lower accuracy) and post it here.
That's why i only asked for "placeholder" and not to mount it by default...
On 7/29/19, prasimix notifications@github.com wrote:
Huh, for $1500 that must be a real stuff! It is also significant that it provides 10 MHz. I do believe that we can start to think of it in foreseeable future, but for the beginning I think that will be much easier to make a whole think attractive with something below $100. I'll try to find something in that price range (and obviously with lower accuracy) and post it here.
-- You are receiving this because you were mentioned. Reply to this email directly or view it on GitHub: https://github.com/prasimix/DIB-v2/issues/8#issuecomment-515931182
Fair enough ;)
@emard, we've discussed about need of master/reference clock for peripheral modules if they have FPGAs deployed since it could be more cost efficient and accurate to introduce master clock on the new master ("CPU") board then to use separate oscillators on each modules and take extra care about inter-module sync. Question is what clock frequency to use (e.g. VXI is using 10 MHz, but ULX3S use 25 MHz) and what price/accuracy class?