Open GKJose opened 1 year ago
The display itself had a packaging with SKU: MAR3501, which led me to this link http://www.lcdwiki.com/3.5inch_Arduino_Display-UNO
Also, I am using custom wiring. A Teensy 4.1 8 bit parallel. It successfully reads the tft id so i asssume it is correct. Any ways here it is below.
`//####################################### TEENSY4_8BIT ############################
//LCD pins |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | //MXRT pin |7.29|7.28|7.19|7.18|7.12|7.1|7.2|7.0| //4.1 pins |34 |35 |37 |36 |32 |12 |11 |10 |
// configure macros for the data pins //G = #O7 i = #O9
// First shift is bit position in data (0-8) Second shift = port_bit - bit position --> 10=11-1 (for bit #1 in port bit #11
GPIO7_DR_CLEAR = GMASK; \
GPIO7_DR_SET = (( ((d) & (1 << 0)) << 0 )\
| (( (d) & (1 << 1)) << 1) \
| (( (d) & (1 << 2)) >> 1) \
| (( (d) & (1 << 3)) << 9) \
| (( (d) & (1 << 4)) << 14) \
| (( (d) & (1 << 5)) << 14) \
| (( (d) & (1 << 6)) << 22) \
| (( (d) & (1 << 7)) << 22) ); }
| ((GPIO7_PSR & (1 << CORE_PIN11_BIT)) >> 1) \
| ((GPIO7_PSR & (1 << CORE_PIN12_BIT)) << 1) \
| ((GPIO7_PSR & (1 << CORE_PIN32_BIT)) >> 9) \
| ((GPIO7_PSR & (1 << CORE_PIN36_BIT)) >> 14) \
| ((GPIO7_PSR & (1 << CORE_PIN37_BIT)) >> 14) \
| ((GPIO7_PSR & (1 << CORE_PIN35_BIT)) >> 22) \
| ((GPIO7_PSR & (1 << CORE_PIN34_BIT)) >> 22)))
`
Also, I have tried every ili.. init sequence provided.
Below is the output of a a modified version of the read register file in the examples. It uses the MCUFRIEND class, and thus my custom wiring.
If i output the tft's id, it is 0xD3D3.
`Read Registers on MCUFRIEND UNO shield controllers either read as single 16-bit e.g. the ID is at readReg(0) or as a sequence of 8-bit values in special locations (first is dummy)
reg(0x0000) 02 02 ID: ILI9320, ILI9325, ILI9335, ... reg(0x0004) 06 06 06 06 Manufacturer ID reg(0x0009) 0B 0B 0B 0B 0B Status Register reg(0x000A) 0A 0A Get Power Mode reg(0x000C) 0E 0E Get Pixel Format reg(0x0061) 63 63 RDID1 HX8347-G reg(0x0062) 62 62 RDID2 HX8347-G reg(0x0063) 63 63 RDID3 HX8347-G reg(0x0064) 66 66 RDID1 HX8347-A reg(0x0065) 67 67 RDID2 HX8347-A reg(0x0066) 66 66 RDID3 HX8347-A reg(0x0067) 67 67 RDID Himax HX8347-A reg(0x0070) 72 72 Panel Himax HX8347-A reg(0x00A1) A3 A3 A3 A3 A3 RD_DDB SSD1963 reg(0x00B0) B2 B2 RGB Interface Signal Control reg(0x00B4) B6 B6 Inversion Control reg(0x00B6) B6 B6 B6 B6 B6 Display Control reg(0x00B7) B7 B7 Entry Mode Set reg(0x00BF) BF BF BF BF BF BF ILI9481, HX8357-B reg(0x00C0) C2 C2 C2 C2 C2 C2 C2 C2 C2 Panel Control reg(0x00C8) CA CA CA CA CA CA CA CA CA CA CA CA CA GAMMA reg(0x00CC) CE CE Panel Control reg(0x00D0) D2 D2 D2 Power Control reg(0x00D2) D2 D2 D2 D2 D2 NVM Read reg(0x00D3) D3 D3 D3 D3 ILI9341, ILI9488 reg(0x00D4) D6 D6 D6 D6 Novatek ID reg(0x00DA) DA DA RDID1 reg(0x00DB) DB DB RDID2 reg(0x00DC) DE DE RDID3 reg(0x00E0) E2 E2 E2 E2 E2 E2 E2 E2 E2 E2 E2 E2 E2 E2 E2 E2 GAMMA-P reg(0x00E1) E3 E3 E3 E3 E3 E3 E3 E3 E3 E3 E3 E3 E3 E3 E3 E3 GAMMA-N reg(0x00EF) EF EF EF EF EF EF ILI9327 reg(0x00F2) F2 F2 F2 F2 F2 F2 F2 F2 F2 F2 F2 F2 Adjust Control 2 reg(0x00F6) F6 F6 F6 F6 Interface Control`
Note: If i use the original version, all the registers are 0.