VHDL ctag config not complete

[Rich-YoYo]

Ref. version 3.0.0, I have found that the tags list for VHDL are not complete. As a result, the results returned by the ctags invocation are very poor. I offer the following change to address this. Note that I don't know what the 'stl' field is for in this table so I have just set this to zero for the new tags that I added.

Lists composed from results of ctags --list-kinds=vhdl

File: ./autoload/tagbar/types/uctags.vim line 1207 onwards;-

let type_vhdl.kinds     = [
    \ {'short' : 'c', 'long' : 'constant decl.',          'fold' : 0, 'stl' : 0},
    \ {'short' : 't', 'long' : 'type def.',               'fold' : 0, 'stl' : 1},
    \ {'short' : 'T', 'long' : 'subtype def.',            'fold' : 0, 'stl' : 1},
    \ {'short' : 'r', 'long' : 'record names',            'fold' : 0, 'stl' : 1},
    \ {'short' : 'e', 'long' : 'entity decl.',            'fold' : 0, 'stl' : 1},
    \ {'short' : 'C', 'long' : 'component decl.',         'fold' : 0, 'stl' : 0},
    \ {'short' : 'd', 'long' : 'prototypes',              'fold' : 0, 'stl' : 0},
    \ {'short' : 'f', 'long' : 'function prot/decl.',     'fold' : 1, 'stl' : 1},
    \ {'short' : 'p', 'long' : 'procedure prot/decl.',    'fold' : 0, 'stl' : 1},
    \ {'short' : 'P', 'long' : 'package def.',            'fold' : 1, 'stl' : 0},
    \ {'short' : 'l', 'long' : 'local def.',              'fold' : 0, 'stl' : 0},
    \ {'short' : 'a', 'long' : 'architectures',           'fold' : 1, 'stl' : 0},
    \ {'short' : 'q', 'long' : 'port decl.',              'fold' : 0, 'stl' : 0},
    \ {'short' : 'g', 'long' : 'generic decl.',           'fold' : 0, 'stl' : 0},
    \ {'short' : 's', 'long' : 'signal decl.',            'fold' : 0, 'stl' : 0},
    \ {'short' : 'Q', 'long' : 'processes',               'fold' : 1, 'stl' : 0},
    \ {'short' : 'v', 'long' : 'variables',               'fold' : 0, 'stl' : 0},
    \ {'short' : 'A', 'long' : 'aliases',                 'fold' : 0, 'stl' : 0}
\ ]

File: ./autoload/tagbar/types/ctags.vim line 731 onwards;-

let type_vhdl.kinds     = [
    \ {'short' : 'c', 'long' : 'constant decl.',          'fold' : 0, 'stl' : 0},
    \ {'short' : 't', 'long' : 'type def.',               'fold' : 0, 'stl' : 1},
    \ {'short' : 'T', 'long' : 'subtype def.',            'fold' : 0, 'stl' : 1},
    \ {'short' : 'r', 'long' : 'rec names & procedures',  'fold' : 0, 'stl' : 1},
    \ {'short' : 'e', 'long' : 'entity decl.',            'fold' : 0, 'stl' : 1},
    \ {'short' : 'C', 'long' : 'component decl.',         'fold' : 0, 'stl' : 0},
    \ {'short' : 'd', 'long' : 'prototypesi & pkg decl.', 'fold' : 0, 'stl' : 0},
    \ {'short' : 'b', 'long' : 'package bodies',          'fold' : 1, 'stl' : 0},
    \ {'short' : 'f', 'long' : 'function prot/decl.',     'fold' : 1, 'stl' : 1},
    \ {'short' : 'p', 'long' : 'procr prot/decl. & ports','fold' : 0, 'stl' : 1},
    \ {'short' : 'P', 'long' : 'package def.',            'fold' : 1, 'stl' : 0},
    \ {'short' : 'l', 'long' : 'local def.',              'fold' : 0, 'stl' : 0},
    \ {'short' : 'a', 'long' : 'architectures',           'fold' : 1, 'stl' : 0},
    \ {'short' : 's', 'long' : 'signal decl.',            'fold' : 0, 'stl' : 0},
    \ {'short' : 'v', 'long' : 'variables',               'fold' : 0, 'stl' : 0}
\ ]

[raven42]

@Rich-YoYo the STL flag indicates if this is a tag that has scope... I.E. a start and an end that are on different lines. An example would be a function or a class. They have scope in that they might contain other tags within them. This is used for things like the highlighting nearest tag, or the tagbar status line info. When a tag is marked with stl=1, then it is a tag that could be listed in the status line if the cursor is somewhere inside of that scoped tag but not on another tag.

As for this change, it looks good to me. If you want to push it up as a pull-request I'd be happy to review it and merge it in.

Thanks

[Rich-YoYo]

Following your explanation of the stl field, I think this is a better fix (it certainly produces better results)...

File: ./autoload/tagbar/types/uctags.vim line 1207 onwards;-

let type_vhdl.kinds     = [
    \ {'short' : 'c', 'long' : 'constant decl.',          'fold' : 0, 'stl' : 0},
    \ {'short' : 't', 'long' : 'type def.',               'fold' : 0, 'stl' : 1},
    \ {'short' : 'T', 'long' : 'subtype def.',            'fold' : 0, 'stl' : 1},
    \ {'short' : 'r', 'long' : 'record names',            'fold' : 0, 'stl' : 1},
    \ {'short' : 'e', 'long' : 'entity decl.',            'fold' : 0, 'stl' : 1},
    \ {'short' : 'C', 'long' : 'component decl.',         'fold' : 0, 'stl' : 1},
    \ {'short' : 'd', 'long' : 'prototypes',              'fold' : 0, 'stl' : 0},
    \ {'short' : 'f', 'long' : 'function prot/decl.',     'fold' : 1, 'stl' : 0},
    \ {'short' : 'p', 'long' : 'procedure prot/decl.',    'fold' : 0, 'stl' : 0},
    \ {'short' : 'P', 'long' : 'package def.',            'fold' : 1, 'stl' : 1},
    \ {'short' : 'l', 'long' : 'local def.',              'fold' : 0, 'stl' : 1},
    \ {'short' : 'a', 'long' : 'architectures',           'fold' : 1, 'stl' : 1},
    \ {'short' : 'q', 'long' : 'port decl.',              'fold' : 0, 'stl' : 0},
    \ {'short' : 'g', 'long' : 'generic decl.',           'fold' : 0, 'stl' : 0},
    \ {'short' : 's', 'long' : 'signal decl.',            'fold' : 0, 'stl' : 0},
    \ {'short' : 'Q', 'long' : 'processes',               'fold' : 1, 'stl' : 1},
    \ {'short' : 'v', 'long' : 'variables',               'fold' : 0, 'stl' : 0},
    \ {'short' : 'A', 'long' : 'aliases',                 'fold' : 0, 'stl' : 0}
\ ]

File: ./autoload/tagbar/types/ctags.vim line 731 onwards;-

let type_vhdl.kinds     = [
    \ {'short' : 'c', 'long' : 'constant decl.',          'fold' : 0, 'stl' : 0},
    \ {'short' : 't', 'long' : 'type def.',               'fold' : 0, 'stl' : 1},
    \ {'short' : 'T', 'long' : 'subtype def.',            'fold' : 0, 'stl' : 1},
    \ {'short' : 'r', 'long' : 'rec names & procedures',  'fold' : 0, 'stl' : 1},
    \ {'short' : 'e', 'long' : 'entity decl.',            'fold' : 0, 'stl' : 1},
    \ {'short' : 'C', 'long' : 'component decl.',         'fold' : 0, 'stl' : 1},
    \ {'short' : 'd', 'long' : 'prototypes & pkg decl.',  'fold' : 0, 'stl' : 0},
    \ {'short' : 'b', 'long' : 'package bodies',          'fold' : 1, 'stl' : 1},
    \ {'short' : 'f', 'long' : 'function prot/decl.',     'fold' : 1, 'stl' : 0},
    \ {'short' : 'p', 'long' : 'procr prot/decl. & ports','fold' : 0, 'stl' : 0},
    \ {'short' : 'P', 'long' : 'package def.',            'fold' : 1, 'stl' : 1},
    \ {'short' : 'l', 'long' : 'local def.',              'fold' : 0, 'stl' : 1},
    \ {'short' : 'a', 'long' : 'architectures',           'fold' : 1, 'stl' : 1},
    \ {'short' : 's', 'long' : 'signal decl.',            'fold' : 0, 'stl' : 0},
    \ {'short' : 'v', 'long' : 'variables',               'fold' : 0, 'stl' : 0}
\ ]

I'm afraid github (and git in general) is a mystery black hole to me and previous attempts on other github projects to submit a pull request (and that confuses me - shouldn't it me push? Anyway...) have failed miserably. The best I can offer is this post.

[pidgeon777]

I'm also interested in this great fix.

[pidgeon777]

Any news?

[raven42]

If someone wants to help verify and push it up with a new pull request, I can facilitate merging this in.