I have tested the D/A and A/D modules at different sample rates, but this is not exposed by the software--everything is 44.1 kHz now. This needs to be fixed.
Tasks:
[x] Build up a new clock board with the "standard" clock configuration (CLK0 = 22.5792 MHz, CLK1 = 24.576 MHz). My board actually has CLK0 = 24.576 MHz and CLK1 = 11.2896 MHz for historical reasons.
[x] Make I2S clock divider adjustable in slot_controller and expose this functionality through the host interface.
[x] Modify Python scripts to accept sample rate as a command line argument and change the clock configuration if necessary before sending audio. (Careful; there might already be samples in the FIFO that need to be played back with the previous sample rate before switching.)
[ ] Evaluate different oscillator types subjectively.
I have tested the D/A and A/D modules at different sample rates, but this is not exposed by the software--everything is 44.1 kHz now. This needs to be fixed.
Tasks: