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pro711 / sublime-verilog

Verilog Package for Sublime Text 2/3
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Missing match #13

Open WZ-Tong opened 4 months ago

WZ-Tong commented 4 months ago

If I write code in this style:

module_name
#(
    .parameter (p_sample)
) inst_module (
    .clk        (clk),
    .rstn       (rstn)
);

the module_name, inst_module field cannot be highlighted