The 'or' operator is no a logical operator according to the Verilog standard.
If you wish to keep it in that category bare in mind that the highlight is buggy since every occurence of the string 'or' is highlighted (eg: as part of a identifier 'factor', the 'or' gets highlighted).
The 'or' operator is no a logical operator according to the Verilog standard. If you wish to keep it in that category bare in mind that the highlight is buggy since every occurence of the string 'or' is highlighted (eg: as part of a identifier 'factor', the 'or' gets highlighted).