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professor-hippo / pyemu

Automatically exported from code.google.com/p/pyemu
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add/fix the ADD/SBB inst #8

Open GoogleCodeExporter opened 9 years ago

GoogleCodeExporter commented 9 years ago 
class PyCPU:
...
    def AND(self, instruction):
...
# <<< added by forc1
        #22 /r AND r8,r/m8 r8  r/m8  
        elif instruction.opcode == 0x22:

            osize = 1

            op1value = self.get_register(op1.reg, osize)

            if op2.type == pydasm.OPERAND_TYPE_REGISTER:
                op2value = self.get_register(op2.reg, osize)

                # Do logic
                result = op1value & op2value

                self.set_flags("LOGIC", op1value, op2value, result, osize)

                self.set_register(op1.reg, result, osize)

            elif op2.type == pydasm.OPERAND_TYPE_MEMORY:
                op2value = self.get_memory_address(instruction, 2, asize)
                op2valuederef = self.get_memory(op2value, osize)

                # Do logic
                result = op1value & op2valuederef

                self.set_flags("LOGIC", op1value, op2valuederef, result, osize)

                self.set_register(op1.reg, result, osize)

            opcode = instruction.opcode
            if opcode in self.emu.opcode_handlers:
                if op1valuederef != None and op2valuederef == None:
                    self.emu.opcode_handlers[opcode](self.emu, opcode, self.get_register32("EIP"), op1valuederef, op2value, op3value)
                elif op2valuederef != None and op1valuederef == None:
                    self.emu.opcode_handlers[opcode](self.emu, opcode, self.get_register32("EIP"), op1value, op2valuederef, op3value)
                else:
                    self.emu.opcode_handlers[opcode](self.emu, opcode, self.get_register32("EIP"), op1value, op2value, op3value)
# >>>

...
    def SBB(self, instruction):
...

# <<< added by forc1
        #1a /r SBB r8,r/m8 Subtract with borrow r/m8 from r8 
        elif instruction.opcode == 0x1a:

            osize = 1

            op1value = self.get_register(op1.reg, osize)

            if op2.type == pydasm.OPERAND_TYPE_REGISTER:
                op2value = self.get_register(op2.reg, osize)

                # Do logic
                result = op1value - (op2value + self.CF)
                oldcf = self.CF

                self.set_flags("SBB", op1value, op2value + self.CF, result, osize)

                if oldcf == 0:
                    self.CF = oldcf

                self.set_register(op1.reg, result, osize)

            elif op2.type == pydasm.OPERAND_TYPE_MEMORY:
                op2value = self.get_memory_address(instruction, 2, asize)

                # Do logic
                op2valuederef = self.get_memory(op2value, osize)

                result = op1value - (op2valuederef + self.CF)
                oldcf = self.CF

                self.set_flags("SBB", op1value, op2valuederef + self.CF, result, osize)

                if oldcf == 0:
                    self.CF = oldcf

                result = self.sanitize_value(result, osize)

                self.set_register(op1.reg, result, osize)

            opcode = instruction.opcode
            if opcode in self.emu.opcode_handlers:
                if op1valuederef != None and op2valuederef == None:
                    self.emu.opcode_handlers[opcode](self.emu, opcode, self.get_register32("EIP"), op1valuederef, op2value, op3value)
                elif op2valuederef != None and op1valuederef == None:
                    self.emu.opcode_handlers[opcode](self.emu, opcode, self.get_register32("EIP"), op1value, op2valuederef, op3value)
                else:
                    self.emu.opcode_handlers[opcode](self.emu, opcode, self.get_register32("EIP"), op1value, op2value, op3value)
# >>>

...
        #1B /r SBB r16,r/m16 Subtract with borrow r/m16 from r16
        #1B /r SBB r32,r/m32 Subtract with borrow r/m32 from r32
        elif instruction.opcode == 0x1b:
...
            elif op2.type == pydasm.OPERAND_TYPE_MEMORY:
                op2value = self.get_memory_address(instruction, 2, asize)

# <<< fixed by forc1
                # Do logic
                #op1valuederef = self.get_memory(op1value, osize)
                op2valuederef = self.get_memory(op2value, osize)

                #result = op1valuederef - (op2value + self.CF)
                result = op1value - (op2valuederef + self.CF)
                oldcf = self.CF

                #self.set_flags("SBB", op1valuederef, op2value + self.CF, result, osize)
                self.set_flags("SBB", op1value, op2valuederef + self.CF, result, osize)

                if oldcf == 0:
                    self.CF = oldcf

                result = self.sanitize_value(result, osize)

                #self.set_memory(op1value, result, osize)
                self.set_register(op1.reg, result, osize)
# >>>
...

Original issue reported on code.google.com by kim.fo...@gmail.com on 27 Oct 2010 at 7:15

GoogleCodeExporter commented 9 years ago 
add/fix the ADD/SBB inst
add/fix the AND/SBB inst -> not 'ADD', but 'AND'

(i don't know how to modify the subject of this issue.)

Original comment by kim.fo...@gmail.com on 27 Oct 2010 at 7:19