Normal use of a clock enable will gate an entire subcircuit. Currently we specify clock enable on individual delays. This means usage of clock gating must be added in advance and explicitly threaded through the interface of circuits into subcircuits. A simpler design would be to write it as a combinator taking a subcircuit clockEnable (subcircuit: x): cava x, gating the entire subcircuit passed in.
blaxill
commented
3 years ago
Normal use of a clock enable will gate an entire subcircuit. Currently we specify clock enable on individual delays. This means usage of clock gating must be added in advance and explicitly threaded through the interface of circuits into subcircuits. A simpler design would be to write it as a combinator taking a subcircuit
clockEnable (subcircuit: x): cava x, gating the entire subcircuit passed in.