#24 linearity/consistency/format revision

[Mingkai-Li]

Issue #24: This PR is trying to move Capstone-RISC-V ISA from the draft version to the 1st releasable version.

• linearity revision
  • linearity is maintained in all instructions and interrupt/exception operations.
  • Sequence of the steps is adjusted so that the data used by steps afterwards won't be overwritten mistakenly (especially in some corner cases).
• consistency revision: Update semantics to the latest version, fix some legacy issues.
• format revision
  • Collapsible blocks are used for explanatory notes.
  • Dark-color blocks are used for instruction exceptions.
  • Light-color blocks are used for instruction execution steps.
• Semantics of control flow instructions and interrupt/exceptions are adjusted
  • The original intention is maintained in this PR.
  • Some unnecessary operations are removed (e.g. store csp and 31 GPRs at the same time).
  • Control flow instructions are adjusted based on interrupt/exceptions for compatibility.
  • RETURN is extended to handle epc and epc is removed from CCSRs (i.e., work as a shadow register).
  • Some obvious bugs are fixed.
  • TODOs are moved to comments.
  • Some places are labeled as FIXME in comments for further consideration.
  • Documentation of debug instructions is removed from the ISA.

[jasonyu1996]

It seems we are not using the right way for cross-references. It does not work in the PDF target. https://docs.asciidoctor.org/asciidoc/latest/macros/xref/

[jasonyu1996]

It seems we are not using the right way for cross-references. It does not work in the PDF target. https://docs.asciidoctor.org/asciidoc/latest/macros/xref/

This has been fixed

[jasonyu1996]

Memory bounds checks for the sealed types should have lowerbound base + 2 * CLENBYTES now (upperbound has been revised to + 33 * CLENBYTES?)

[jasonyu1996]

In a few places the current description of the semantics does not work properly if the register operands overlap. Need to revise and fix those as well

[jasonyu1996]

Memory bounds checks for the sealed types should have lowerbound base + 2 * CLENBYTES now (upperbound has been revised to + 33 * CLENBYTES?)

This has been fixed

[Mingkai-Li]

Memory bounds checks for the sealed types should have lowerbound base + 2 * CLENBYTES now (upperbound has been revised to + 33 * CLENBYTES?)

In interrupt/exception, csp is not sealed because we are going to seal 31 GPRs anyway. But for memory access granted by sealed-return and exit capability, because it's synchronous, csp in going to be sealed and unsealed automatically. Therefore, we don't need to give additional access to this memory region.

So, the lowerbound is base + 3 * CLENBYTES, while the upperbound is base + 33 * CLENBYTES.

[Mingkai-Li]

Also, there are some FIXMEs in the comment. Please take a look if you are available. :smiley:

[jasonyu1996]

Yea it was + 3 * CLENBYTES earlier. Now fixed

[jasonyu1996]

The current draft good to me. But @Mingkai-Li perhaps you can explain those FIXMEs in a commit/comments. After addressing those let's just merge