GPIO chassis defines two modes for delivering GPIO interrupts, namely the legacy GPIO interrupt (GPI) mode and IOAPIC interrupt mode. Both modes deliver GPIO input events as INTx to the host SW. With the GPIO chassis being exposed to the safety VM, the GPIO interrupts shall be properly forwarded to the same VM as well. The safety VM shall be able to control how such interrupts are delivered by programming IOAPIC RTEs.
It is required that the interrupt line triggered by an GPIO event is consistent with the one programmed in the PAD configuration register from VM's perspective. It is NOT, however, enforced that it is the same as the host interrupt line.
donsheng
commented
4 years ago
GPIO chassis defines two modes for delivering GPIO interrupts, namely the legacy GPIO interrupt (GPI) mode and IOAPIC interrupt mode. Both modes deliver GPIO input events as INTx to the host SW. With the GPIO chassis being exposed to the safety VM, the GPIO interrupts shall be properly forwarded to the same VM as well. The safety VM shall be able to control how such interrupts are delivered by programming IOAPIC RTEs. It is required that the interrupt line triggered by an GPIO event is consistent with the one programmed in the PAD configuration register from VM's perspective. It is NOT, however, enforced that it is the same as the host interrupt line.
[External_System_ID]ACRN-6625