At the price of one extra flipflop (last_h_stitch0) I extended h-line by one pixel.
Code is in verilog due to the the fact that I use ISE with basys2 to play with VGA :)
Thank you for this excellent suggestion! 🙏
I have created a branch for this fix and successfully tested it in simulation. Once I've tested on boards I'll merge.
At the price of one extra flipflop (last_h_stitch0) I extended h-line by one pixel. Code is in verilog due to the the fact that I use ISE with basys2 to play with VGA :)