Closed WillGreen closed 7 months ago
Initial port of FPGA Graphics to ULX3S.
1280x720p60 display with 74 MHz pixel clock (should be 74.25 MHz, but 74 MHz is within spec that allows for ±0.5%).
Reset button does nothing at the moment: I probably need to read up on the PLL some more.
Initial port of FPGA Graphics to ULX3S.
1280x720p60 display with 74 MHz pixel clock (should be 74.25 MHz, but 74 MHz is within spec that allows for ±0.5%).
Reset button does nothing at the moment: I probably need to read up on the PLL some more.