Netlist issues from klayout

proppy / conda-eda

Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.

https://anaconda.org/LiteX-Hub

Apache License 2.0

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Netlist issues from klayout #2

Open spnadig opened 1 year ago

spnadig commented 1 year ago

Netlist generated by klayout while running LVS generates .cir file. The .cir netlist's terminal order for (say for transistor) does not match the terminal order of xschem's netlist for same transistor (nfet, pfet). This causes LVS error in Klayout. Need a script to correct terminal order in .cir with ones in .cdl

proppy commented 1 year ago

That probably something to report against https://github.com/KLayout/klayout, but I don't think it affect the LVS checks anymore as we got the device properly imported from xschem now that https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_pr/issues/101 is fixed.