Using all 38 I/O pins

[browndeer]

Attempting to use 19 input and 19 output pins produces an error. I beleive the correct fix is shown below. This appeared to produce the correct mapping and passed GDS.

--- configure.py.old 2022-12-08 09:57:00.976000000 -0500 +++ configure.py.new 2022-12-08 09:57:40.285000000 -0500 @@ -11,7 +11,7 @@ import re import jinja2

-GPIO_VALID_RANGE = [8, 36] +GPIO_VALID_RANGE = [0, 38]

def load_yaml(yaml_file): with open(yaml_file, "r") as stream:

--- tiny_user_project.v.jinja2.old 2022-12-08 09:58:42.992000000 -0500 +++ tiny_user_project.v.jinja2.new 2022-12-08 09:58:27.976000000 -0500 @@ -45,7 +45,7 @@ io_out[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}] ); // all output enabled -assign io_oeb[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}] = 8'b0; +assign io_oeb[{{ io_out_range[1] - 1 }}:{{ io_out_range[0] }}] = 'd0;

endmodule // tiny_user_project

[proppy]

It should be safe to use pins starting from 5 but my understanding is that 0-4 are reserved, see the comment here: https://github.com/proppy/tiny_user_project/blob/main/verilog/rtl/user_defines.v.jinja2#L43

[browndeer]

Thanks for clarifying. Does this mean that the configuration of pins 0-4 cannot be changed, or that they cannot be used (as input) in any way? It appeared to me that those pins were configured as inputs, but I am just getting familiar with this stuff. Thanks.

[rolfmobile99]

Hi Proppy and browndeer, Reading carefully that comment in user_defines.v.jinja2 suggests that you shouldn't change the configuration of GPIO pins 0-4, but maybe you can still use them? If so, a short piece of code running on the caravel RISC-V should be able to update the configuration of those pins. But that is after power-up and running some code. So this may or may not be practical for your design. My 2 cents... -Rolf