Fix invalid AXI write data valid when no AXI write is active

proteus-core / proteus

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

MIT License

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Fix invalid AXI write data valid when no AXI write is active #6

Closed eyck closed 1 year ago

eyck commented 1 year ago

The W channel (of the dbus) gets a valid even when AW channel is not active. This violates the AXI spec and this PR fixes it.

martonbognar commented 1 year ago

Nice find, thanks! (And by now the GitHub actions are also fixed :) To be clear, this is unrelated to #5, right?

eyck commented 1 year ago

Yes, it is unrelated to #5. Actually I integrated the core in our SystemC UVM testbench to run a few tests and performacne measures. And our adapters were complaining...

martonbognar commented 1 year ago

Nice! Any interesting results you can share? :)

eyck commented 1 year ago

Not really. I did run a dhrystone on it and was wondering why the dynamic version achieves only ~0.7 DMIPS/MHz. I would have expect something beyond 1DMIPS/Mhz... But I did not do any further investigations.