New assembler thinks instruction cvt.w.s isn't supported

[F0bes]

Try to assemble something like cvt.w.s $f12, $f12 Which should use the FPU coprocessor

When assembled I get met with this: Error: opcode not supported on this processor: r5900 (mips3) 'cvt.w.s $f12,$f12'

This instruction is supported on the r5900 as shown from the instruction manual:

Edit: This probably should have went to the ps2toolchain-ee repo (oops)

[rickgaiser]

It should be supported. The following line in binutils defines the opcode: https://github.com/ps2dev/binutils-gdb/blob/ee-v2.36.0/opcodes/mips-opc.c#L1012 In the old toolchain defined here: https://gitlab.com/ps2max/toolchain/binutils/-/blob/ps2-v2.14/opcodes/mips-opc.c#L487

I'll try testing this when I have some time.

[davidgfnet]

Was reading the EE and MIPS32 manuals. Seems like cvt.w.s is a valid instruction on both CPUs and has the same encoding right? However EE does not have a trunc.w.s instruction, right? If I'm reading this correctly the binutils 2.14 were just assuming that, for the EE, cvt and trunc are just synonims (encode the same instruction, so adding truncate is the same as adding cvt). However in the new version of binutils, even though we also have the trunc->cvt synonym, it seems like cvt is excluded for the EE target. This is weird. If anything I'd say "truncate" should be disabled (not cvt) since it doesn't show up in the manual. Perhaps it is enabled as a synonym just in case gcc uses it. This all seems to stem from the fact that PS2 does not do any rounding from the looks of it and always truncates FPs?

[fjtrujy]

I think that the problem as @davidgfnet pointed it out, is that specific instruction, https://github.com/ps2dev/binutils-gdb/blob/ee-v2.36.0/opcodes/mips-opc.c#L1012 was being excluded from EE CPU.

Maybe this PR works, https://github.com/ps2dev/binutils-gdb/pull/1 @F0bes could you take a look?

Thanks

[uyjulian]

Fixed by https://github.com/ps2dev/binutils-gdb/commit/abfee97a884692cf292f1cddd5079515bde57b5e