Open fedy2 opened 2 years ago
The signals values are transmitted "backwards" to PulseView.
PulseView expects the data to be in reverse order (OLS implementation of SUMP): https://github.com/sigrokproject/libsigrok/blob/master/src/hardware/openbench-logic-sniffer/protocol.c#L499
Similar discussion in the logic analyzer for Arduino: issue #38
The signals values are transmitted "backwards" to PulseView.
PulseView expects the data to be in reverse order (OLS implementation of SUMP): https://github.com/sigrokproject/libsigrok/blob/master/src/hardware/openbench-logic-sniffer/protocol.c#L499
Similar discussion in the logic analyzer for Arduino: issue #38