hello. i am interesting with the project. but module "ulpi_bulk_axis" is not found.thanks

psuggate / axi-ddr3-lite

AXI DDR3 SDRAM Memory Controller for Xilinx GoWin Altera Intel Lattice FPGAs, written in Verilog.

MIT License

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Open allrighteveryday opened 4 months ago

allrighteveryday commented 4 months ago

hello. i am interested in the project. but module "ulpi_bulk_axis" is not found.thanks

psuggate commented 4 months ago

Sorry. I'm currently developing this in a different repo (https://github.com/psuggate/misc-verilog-cores), and it's still not ready.