"Cannot find a driver for bit" error with simple pass-through verilog

[th-in-gs]

I'm not sure if this is something intrinsic to the properties of a GAL, but I'm unable to PNR a simple pass-through module.

Files I'm using:

module top(i_sw, o_led);
    input wire i_sw;
    output wire o_led;

    assign o_led = i_sw;
endmodule

device: GAL16V8
mode: simple 
pins:
    i_sw: 2
    o_led: 18

Command line:

~/D/V/T/01-thruwire> regal build -o thruwire.jed device.yaml thruwire.v
[ERROR][regal_pnr] Cannot find a driver for bit 2

I'm new both to verilog and GALs, but if feels like this should be possible.

If I change this to do something more complex - even just negating the input - it works.

thruwire.zip

[th-in-gs]

So, what's happening here is that, in the generated netlist, the input is directly connected to the output instead of going through one of the SOP elements. The PNR phase doesn't like that.

I could swear that when I was playing around with this last weekend, I was able get this to work by removing one of the 'opt' stages passed to yosys by synth.py - doing this caused the SOP stage to be included even for this 'buffer' - but now that I come back to it a week later, that's not working, I'm getting errors as above again.