psurply / ReGAL

A set of scripts used to assist reverse engineering of old-school Programmable Array Logic devices.
MIT License
66 stars 7 forks source link

Signal is discarded #6

Closed ladmanj closed 1 year ago

ladmanj commented 1 year ago

Hello, I actually don't know whether it's bug or user mistake, but my design gets not compiled as expected. Please see attached source and output files

Everything works OK (even in physical device) but the NMR signal is discarded for an unknown reason.

Thanks for help

JL

module top (
input  A10,A11,A12,A13,A14,A15,NIOR,NIOW,IOW,NMR,
output MW,MR,G,RAM
);

wire [7:0] adr;

reg RAM;

always @(posedge IOW ) begin
    if(adr == 8'hfc) RAM <= 1'b1;
    else 
    if(adr == 8'hf8) RAM <= 1'b0;
end

assign MW = ~NIOW;
assign G = (adr == 8'h24) | (adr == 8'h28) | (adr == 8'h2c) | (adr == 8'h30) | ((adr == 8'h00) & RAM & NIOR & NIOW); 

assign MR = (~NIOR & ((adr == 8'h24) | (adr == 8'h28) | (adr == 8'h2c) | (adr == 8'h30))) | ((adr == 8'b00000XXX) & ~(NMR | RAM));
assign adr = {A15,A14,A13,A12,A11,A10,2'b00};
endmodule

image whatabout.tar.gz

ladmanj commented 1 year ago

Hi, The problem is at least partly resolved, the NMR signal was discarded as dependent on the (adr == 8'b00000XXX) comparison. Probably the "don't care" X's are not supported by the hardware or what ever.

Thanks

ladmanj commented 1 year ago

If the author of ReGAL wants to investigate it, I'm going to help as I can. But my problem is now solved by design change. I'm closing the issue. Thanks