Skip fails to open PCB files if they were saved from Kicad V8. The parser returns the same error when using skip as a library in another script or interactively in a REPL session. Kicad V7 PCBs open correctly. Schematics also open correctly from both V7 and V8 files.
Example error:
pcb8 = skip.PCB("C:\Dev\myProject\Control Board\LEDTest_controlboard_8.kicad_pcb")
Traceback (most recent call last):
File "<stdin>", line 1, in <module>
File "C:\Users\thisUser\AppData\Local\Programs\Python\Python310\lib\site-packages\skip\pcbnew\pcb\pcb.py", line 53, in __init__
super().__init__(filepath)
File "C:\Users\thisUser\AppData\Local\Programs\Python\Python310\lib\site-packages\skip\sexp\sourcefile.py", line 89, in __init__
self.read(filepath)
File "C:\Users\thisUser\AppData\Local\Programs\Python\Python310\lib\site-packages\skip\sexp\sourcefile.py", line 197, in read
entities = list(map(lambda baseobj: wrapClass(baseobj), v))
File "C:\Users\thisUser\AppData\Local\Programs\Python\Python310\lib\site-packages\skip\sexp\sourcefile.py", line 197, in <lambda>
entities = list(map(lambda baseobj: wrapClass(baseobj), v))
File "C:\Users\thisUser\AppData\Local\Programs\Python\Python310\lib\site-packages\skip\pcbnew\footprint.py", line 72, in __init__
footprint_text.append(FootprintText(fptxt))
File "C:\Users\thisUser\AppData\Local\Programs\Python\Python310\lib\site-packages\skip\pcbnew\footprint.py", line 59, in __init__
super().__init__(pv)
File "C:\Users\thisUser\AppData\Local\Programs\Python\Python310\lib\site-pack
ages\skip\sexp\parser.py", line 618, in __init__
for i in pv._base_coords:
AttributeError: 'Symbol' object has no attribute '_base_coords'
Skip fails to open PCB files if they were saved from Kicad V8. The parser returns the same error when using skip as a library in another script or interactively in a REPL session. Kicad V7 PCBs open correctly. Schematics also open correctly from both V7 and V8 files.
Example error:
Tested on:
Test files: LED_BOARD_REFv8.zip created in KicadV8 - fails to open
I'm not sure what _base_coords is so creating them in place or wrapping this bit in a try-catch doesn't seem sensible.
Anything that can be done the file PCB files to make them readable? (rather than changing the skip code).