[RV64_DYNAREC] Added more 66 0F opcodes for vector

ptitSeb / box64

Box64 - Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices

https://box86.org

MIT License

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[RV64_DYNAREC] Added more 66 0F opcodes for vector #1815

Closed ksco closed 2 months ago

ptitSeb commented 2 months ago

All red on the CI! The sse tests all failed.

ksco commented 2 months ago

yeah sorry, it fails with vlen=256 on the newly added packuswb, I've only handled and tested vlen=128, need to think about another way... :(

ptitSeb commented 2 months ago

Well, you can keep the method for when vlen>=256 anyway, and put a method when vlen=128 by spiliting the operation in 2 64bits expensions...

ksco commented 2 months ago

fixed vlen>=256 cases above, 3 more instructions are needed. the packuswb opcode is tricky because we use the narrowing instruction vnclipu.wv, which doubles the LMUL on source registers (i.e. 2 registers form a group). but if vlen>=256, there is no need for a register group....

ptitSeb commented 2 months ago

Strange that vlen>=256 needs more opcodes then shorter vlen... But ok.