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ptitSeb / box64

Box64 - Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices
https://box86.org
MIT License
3.73k stars 267 forks source link

About emulating AVX instructions on RISC-V #1873

Open zohanzephyr opened 2 days ago

zohanzephyr commented 2 days ago

Now that RISC-V dynarec supports vector instructions, will AVX be emulated with scalar instructions?

ksco commented 2 days ago

We need to refine current RVV support, add MMX support for RVV, and add xtheadvector support... so AVX will come after.

zohanzephyr commented 2 days ago

We need to refine current RVV support, add MMX support for RVV, and add xtheadvector support... so AVX will come after.

Will that be followed up by emulating AVX with RISC-V scalar instructions? Isn't it enough to use RVV

ptitSeb commented 2 days ago

There is always the interpreter when opcodes are not implemented in the dynarec.

Idealy, the dynarec would run on all CPU, so scalar as a minimum, rvv/xthreadvector if available. But it's a mater of time/work. It's still a lot of work to implement all those opcodes.

What are you interested in with AVX emulation @zohanzephyr ?

zohanzephyr commented 2 days ago

There is always the interpreter when opcodes are not implemented in the dynarec.

Idealy, the dynarec would run on all CPU, so scalar as a minimum, rvv/xthreadvector if available. But it's a mater of time/work. It's still a lot of work to implement all those opcodes.

What are you interested in with AVX emulation @zohanzephyr ?

I noticed that an application I was running utilized AVX instructions, so I'm interested in learning more about this and any related future plans.