[RV64_DYNAREC] How to View Register Values at Runtime and Set Breakpoints in RISC-V Target Code?

[wangguidong1999]

I'm currently trying to modify the translation logic of some RISC-V instructions, but I encounter errors in the computation results when running test programs. To diagnose the issue, I’d like to observe the state of RISC-V registers at a specific point during execution. I have the following questions:

1. How can I view the RISC-V register values of the translated target code at a specific moment during runtime?
2. Is it possible to set breakpoints in the RISC-V target code, so I can pause execution midway and facilitate debugging?

I'm looking for straightforward methods (e.g., using debugging tools) to accomplish this or any recommended techniques to check the real-time state of registers.

[ptitSeb]

You need to use gdb, that's the only way to see nagtive registers values.

To set a breakpoint in emited code, instert an UDF() which will trigger a SIGILL. Then from gdb do

handle SIGILL nopass
set $pc+=4

so the SIGILL will not be passed to the program, and you skip the UDF code. You can now step by steap and looks at native register. Note that box64 will generate a few SIGILL on purpose at the start of the program, to detect available extension, so do not do the handle command too early.

Good luck with your debugging.

(may I ask what opcodes are you adding?)