Open radomirvr opened 1 month ago
This is not expected behavior. I had some issues with 10 MHz reference clock when I tried to port newer code with X440 support, but this older design should meet timing requirements. I'll try to run the build on this code again.
I got also failure to meet timing requirements. Thank you for reporting this issue. I'll try to find out where it came from.
First of all, many thanks this great port!
Issue Description
I'm trying to make the bitstream, but the design fails to meet the timing requirements by around 80 ps. Most of the paths are inter clock, between the
rfdc_clk_x411_ps_rfdc_bd_data_clock_mmcm_0
and therfdc_clk_2x_x411_ps_rfdc_bd_data_clock_mmcm_0
clock. I'm attaching the timing summary below.The original ettus design (tag
v4.4.0.0
, commit5fac246
) passes timing successfully.Should the design pass the timing or is this perhaps expected?
Setup Details
x411
branch (commitf2901c6
)X411_X4_200
designExpected Behavior
Timing pass.
Actual Behaviour
Timing closure failed:
Steps to reproduce the problem
Additional Information
post_route_timing_summary.log