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pulp-platform / ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
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[VCS] How to run ara on VCS (or irun) ? #169

Open Heresyrac opened 2 years ago

Heresyrac commented 2 years ago

I am trying to move ara on VCS, but met too many errors, and they are hard to fix. Do you have the correct Compilation Options on VCS or irun? Or a script of running by VCS?

These are examples of errors:

`Error-[MNOLIR] Maximum number of loop iterations /data/huangzixuan/workspace/vdk/venv/ara/ara_test/run/dut/ara/ara_test/hardware/deps/common_cells/src/cf_math_pkg.sv, 43 "for (ceil_div = 0; (remainder > 64'sh0000000000000000); ceil_div += 1) begin remainder = (remainder - divisor); end" Maximum number of loop iterations reached in function evaluation. Current maximum: 10000000 Please use '-Xfe_max_loop_iterations=' as work around.

Error-[CECFC] Cannot evaluate constant function call /data/huangzixuan/workspace/vdk/venv/ara/ara_test/run/dut/ara/ara_test/hardware/deps/axi/src/axi_lite_regs.sv, 144 "ceil_div(RegNumBytes, AxiStrbWidth)" The constant function call could not be evaluated during elaboration. Source info: ceil_div(RegNumBytes, AxiStrbWidth) Please check function arguments and function body for non-constant expressions, hierachical references or non-supported constructs

Error-[CEPO] Cannot evaluate parameter override /data/huangzixuan/workspace/vdk/venv/ara/ara_test/run/dut/ara/ara_test/hardware/deps/axi/src/axi_lite_regs.sv, 144 The parameter override should be an expression containing only constant numbers and previously defined parameters. The override was applied to parameter 'NumChunks' of instance 'axi_lite_regs_intf.i_axi_lite_regs'. Source info: ceil_div(RegNumBytes, AxiStrbWidth)

Error-[MNOLIR] Maximum number of loop iterations /data/huangzixuan/workspace/vdk/venv/ara/ara_test/run/dut/ara/ara_test/hardware/deps/common_cells/src/cf_math_pkg.sv, 43 "for (ceil_div = 0; (remainder > 64'sh0000000000000000); ceil_div += 1) begin remainder = (remainder - divisor); end" Maximum number of loop iterations reached in function evaluation. Current maximum: 10000000 Please use '-Xfe_max_loop_iterations=' as work around.

Error-[CECFC] Cannot evaluate constant function call /data/huangzixuan/workspace/vdk/venv/ara/ara_test/run/dut/ara/ara_test/hardware/deps/axi/src/axi_lite_regs.sv, 144 "ceil_div(RegNumBytes, AxiStrbWidth)" The constant function call could not be evaluated during elaboration. Source info: ceil_div(RegNumBytes, AxiStrbWidth) Please check function arguments and function body for non-constant expressions, hierachical references or non-supported constructs

Error-[CEPO] Cannot evaluate parameter override /data/huangzixuan/workspace/vdk/venv/ara/ara_test/run/dut/ara/ara_test/hardware/deps/axi/src/axi_lite_regs.sv, 144 The parameter override should be an expression containing only constant numbers and previously defined parameters. The override was applied to parameter 'NumChunks' of instance 'axi_lite_regs_intf.i_axi_lite_regs'. Source info: ceil_div(RegNumBytes, AxiStrbWidth)`

jin8495 commented 1 year ago

Hello, do you have any progression?

jamesningd commented 1 year ago

I also want to run it with VCS. Did you success to run it with VCS?

takeshineshiro commented 1 year ago

use this makefile content like below to replace the makefile in haredware directory:

Copyright 2021 ETH Zurich and University of Bologna.

Solderpad Hardware License, Version 0.51, see LICENSE for details.

SPDX-License-Identifier: SHL-0.51

#

Author: Matheus Cavalcante matheusd@iis.ee.ethz.ch

SHELL = /usr/bin/env bash ROOT_DIR := $(patsubst %/,%, $(dir $(abspath $(lastword $(MAKEFILE_LIST))))) ARA_DIR := $(shell git rev-parse --show-toplevel 2>/dev/null || echo $$ARA_DIR)

INSTALL_DIR := $(abspath $(ROOT_DIR)/../install)

INSTALL_DIR :=/project/STPU2/wanghaisheng/ara/install

VERILATOR_INCLUDE := $(INSTALL_DIR)/verilator/share/verilator/include/vltstd

Choose Ara's configuration

ifndef config ifdef ARA_CONFIGURATION config := $(ARA_CONFIGURATION) else config := default endif

endif

Include configuration

config_file := $(ROOT_DIR)/../config/$(config).mk include $(abspath $(ROOT_DIR)/../config/$(config).mk)

Clang flags for Verilator command

ifneq (${CLANG_PATH},) CLANG_CXXFLAGS := -CFLAGS "-nostdinc++ -isystem $(CLANG_PATH)/include/c++/v1" CLANG_LDFLAGS := -LDFLAGS "-L $(CLANG_PATH)/lib -Wl,-rpath,$(CLANG_PATH)/lib -lc++ -nostdlib++" else CLANG_CXXFLAGS := "" CLANG_LDFLAGS := "" endif

export ARA_ROOT=$(abspath pwd/../../)

vcs env

export SNPS_AMBA_VIP_HOME=/nfs54/EDA/vip/snps_axi4 export SNPS_AMBA_VIP_HOME=/nfs54/project/SoCVIP/snps_vip_svtb export UVM_HOME=/EDA/synopsys/vcs-mx/N-2017.12-SP2/etc/uvm-1.2 export VERDI_HOME=/EDA/synopsys/verdi/Q-2020.03-SP2-4 MODE = COV_OPT += line+fsm+tgl+cond

NR_LANES=4 VLEN=4096

ifeq ( ${ARA_CONFIGURATION},4_lanes) NR_LANES=4 VLEN=4096 else ifeq(${ARA_CONFIGURATION},2_lanes) NR_LANES=4 VLEN=2048 else ifeq(${ARA_CONFIGURATION},8_lanes) NR_LANES=8 VLEN=8192 else ifeq(${ARA_CONFIGURATION},16_lanes) NR_LANES=16 VLEN=16384 else NR_LANES=4 VLEN=4096

endif

-ntb_opts uvm -full64

COM_OPT = -l ./compile.log -Mdir=./csrc \ -full64 \ -sverilog \ +v2k \ +vcs+initreg+random \ +define+UVM_PACKER_MAX_BYTES=1500000 \ +define+UVM_DISABLE_AUTO_ITEM_RECORDING \ +plusarg_save \ -timescale=1ns/1ps \ -debug_access+all \ -debug_access+report -debug_region=cell+encrypt -notice \ -fsdb \ +define+SVT_UVM_TECHNOLOGY \ +define+SYNOPSYS_SV \ +define+WAVES_DVE \ +define+WAVES="dve" \ +define+TSMC_CM_UNIT_DELAY \ +define+TSMC_CM_NO_WARNING \ +define+NR_LANES=${NR_LANES} \ +define+RVV_ARIANE=1 \ +define+TARGET_ARA_TEST \ +define+TARGET_ASIC \ +define+TARGET_CVA6_TEST \ +define+TARGET_RTL \ +define+TARGET_SIMULATION \ +define+TARGET_VSIM \ +define+VLEN=${VLEN}\ +define+WT_DCACHE=1 \ +define+VCD_DUMP +mode=${MODE} \ -kdb \ -lca \ -Wupdate \ +define+PERF_EN \ +error+1000 \ +define+RAM_AS_REG \ +define+FUNC_SIM \ -error \ -o simv \ +lint=TFIPC-L\ +lint=PCWM

COM_OPT_BACK = -l ./compile.log -Mdir=./csrc \ -full64 \ -sverilog \ -partcomp -fastpartcomp=j2 \ +define+UVM_PACKER_MAX_BYTES=1500000 \ +define+UVM_DISABLE_AUTO_ITEM_RECORDING \ +plusarg_save \ -timescale=1ns/1ps \ -debug_access+all -fgp\ -debug_region=cell+encrypt -notice \ -work mylib \ +define+SVT_UVM_TECHNOLOGY \ +define+SYNOPSYS_SV \ +define+WAVES_DVE \ +define+WAVES="dve" \ +define+TSMC_CM_UNIT_DELAY \ +define+TSMC_CM_NO_WARNING \ +mode=${MODE} \ -kdb \ -lca \ -Wupdate \ +define+PERF_EN \ +error+1000 \ +define+RAM_AS_REG \ +define+FUNC_SIM \ +define+NOC_SIM \ -cm $(COV_OPT) \ -o simv \ +lint=TFIPC-L\ +lint=PCWM

RUN_OPT = -top ara_tb \ +vcs+initreg+0 \ +mode=${MODE} \ -l ./simv.log

-fgp=num_threads:4

build path

buildpath ?= build resultpath ?= results

questa library

library ?= work

dpi library

dpi_library ?= work-dpi

verilator library

veril_library ?= $(buildpath)/verilator

verilator path

veril_path ?= $(abspath $(INSTALL_DIR)/verilator/bin)

verilator top-level

veril_top ?= ara_tb_verilator

Top level module to compile

top_level ?= ara_tb

Questa version

ifeq ($(vcd_dump), 1)

questa_version ?= 2019.3

else

questa_version ?= 2021.2

endif

QuestaSim command

questa_cmd ?= questa-$(questa_version)

QuestaSim arguments

questa_args ?=

Path to the binaries

app_path ?= $(abspath $(ROOT_DIR)/../apps/bin)

Path to ideal dispatcher vtraces

vtrace_path ?= $(abspath $(ROOT_DIR)/../apps/ideal_dispatcher/vtrace)

ara_dpi_path ?= $(abspath $(ROOT_DIR)/../hardware/build/work-dpi) ideal ?= ifeq ($(ideal_dispatcher), 1) vtrace = $(vtrace_path)/$(app).vtrace bender_defs += --define IDEAL_DISPATCHER=1 --define VTRACE="$(vtrace)" --define N_VINSN=$(shell wc -l $(vtrace) | cut -d " " -f 1) ideal = "_ideal" endif

ifeq ($(vcd_dump), 1) vcd_path ?= ../vcd/$(app).vcd bender_defs += --define VCD_DUMP=1 --define VCD_PATH=$(vcd_path) endif

Check if the specified QuestaSim version exists

ifeq (, $(shell which $(questa_cmd)))

Spaces are needed for indentation here!

$(warning "Specified QuestaSim version ($(questa_cmd)) not found in PATH $(PATH)") questa_cmd = endif

questa_args += +UVM_NO_RELNOTES

preload ?= "$(app_path)/hello_world.ideal"

ifdef app ifeq ($(ideal_dispatcher), 1) preload ?= "$(app_path)/$(app).ideal" else preload ?= "$(app_path)/$(app)" endif endif ifdef preload questa_args += +PRELOAD=$(preload) # load binary to tb.sv by wong 2023/02/08 endif questa_args += -sv_lib ${ara_dpi_path}/ara_dpi -voptargs=+acc

questa_args += -suppress vsim-3009 -suppress vopt-7033

DPI source files

dpi := $(patsubst tb/dpi/%.cc,$(buildpath)/$(dpi_library)/%.o,$(wildcard tb/dpi/*.cc))

vlog_args += -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 vlog_args += -work $(library)

Defines

bender_defs += --define NR_LANES=$(nr_lanes) --define VLEN=$(vlen) --define RVV_ARIANE=1

Default target

all: compile

Build path

$(buildpath): mkdir -p $(buildpath)

Bender

bender: @[ -x ./bender ] && echo "Bender already exists." || \ curl --proto '=https' --tlsv1.2 https://fabianschuiki.github.io/bender/init -sSf | sh -s -- 0.23.1 @echo "$$(./bender --version) available."

Patches

.PHONY: apply-patches apply-patches: patches cd deps/tech_cells_generic && git apply ../../patches/0001-tech-cells-generic-sram.patch

Library

.PHONY: lib lib: $(buildpath) $(buildpath)/$(library) $(buildpath)/$(library): cd $(buildpath)&& rm -rf work_vcs/*

Compilation

.PHONY: compile compileback: dpi lib $(buildpath) bender $(buildpath)/compile$(config).tcl $(buildpath)/compile_$(config).tcl: $(config_file) Makefile ../Bender.yml $(shell find src -type f) $(shell find ../config -type f) $(shell find include -type f) $(shell find tb -type f) $(shell find deps -type f) ./bender script vsim --vlog-arg="$(vlog_args)" -t rtl -t asic -t ara_test -t cva6_test $(benderdefs) > $(buildpath)/compile$(config).tcl echo "exit" >> $(buildpath)/compile_$(config).tcl cd $(buildpath) && $(questacmd) vsim -work $(library) -c -do compile$(config).tcl

Remove the file if compilation did not succeed

if [ `cat $(buildpath)/transcript | grep "\*\* Error" | wc -l` -ne 0 ]; then rm $(buildpath)/compile_$(config).tcl; fi

clean_simv: rm -rf ./novas rm -rf ./run.fsdb rm -rf ./csrc rm -rf ./simv

compile: dpi lib $(buildpath)
vcs $(COM_OPT) -top ara_tb +libext+.v -f rtl_cmod.f -assert svaext

vlogan: vlogan -sverilog -full64 -timescale=1ns/1ps -top ara_tb -f rtl_cmod.f -assert svaext -l vlogan.log

compiletest: dpi lib $(buildpath) bender $(buildpath)/compile$(config).tcl $(buildpath)/compile_$(config).tcl: $(config_file) Makefile ../Bender.yml $(shell find src -type f) $(shell find ../config -type f) $(shell find include -type f) $(shell find tb -type f) $(shell find deps -type f) ./bender script vcs $(COM_OPT) -t rtl -t asic -t ara_test -t cva6_test $(benderdefs) > $(buildpath)/compile$(config).tcl echo "exit" >> $(buildpath)/compile_$(config).tcl

Simulation

.PHONY: sim sim_back: compile cd $(buildpath) && \ $(questa_cmd) vsim $(questa_args) $(library).$(top_level) -do ../scripts/run$(ideal).tcl ./scripts/return_status.sh $(buildpath)/transcript

sim: ./simv $(questa_args) $(RUN_OPT)

verdi: verdi -top $(top_level) -f rtl_cmod.f +libext+.v +libext+.sv +libext+.svh -ssf run.fsdb -sv -full64 &

.PHONY: simc simc_back: compile cd $(buildpath) && \ $(questa_cmd) vsim -c $(questa_args) $(library).$(top_level) -do "run -a" ./scripts/return_status.sh $(buildpath)/transcript

RISC-V Tests simulation

APPS_DIR := $(abspath $(ROOT_DIR)/../apps) TESTS_DIR := $(APPS_DIR)/riscv-tests/isa include $(APPS_DIR)/common/riscv_tests.mk

tests := $(ara_tests) $(cva6_tests)

Verilator

.PHONY: verilate verilate: $(buildpath) bender $(veril_library)/V$(veril_top)

$(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell find src -type f) $(shell find ../config -type f) $(shell find include -type f) $(shell find tb -type f) $(shell find deps -type f) rm -rf $(veril_library); mkdir -p $(veril_library) ./bender script verilator -t rtl -t ara_test -t cva6_test -t verilator $(bender_defs) > $(veril_library)/benderscript$(config)

Verilate the design

$(veril_path)/verilator -f $(veril_library)/bender_script_$(config)           \

-GNrLanes=$(nr_lanes) \ -O3 \ -Wno-BLKANDNBLK \ -Wno-CASEINCOMPLETE \ -Wno-CMPCONST \ -Wno-LATCH \ -Wno-LITENDIAN \ -Wno-UNOPTFLAT \ -Wno-UNPACKED \ -Wno-UNSIGNED \ -Wno-WIDTH \ -Wno-WIDTHCONCAT \ --hierarchical \ --trace \ tb/verilator/waiver.vlt \ --Mdir $(veril_library) \ -Itb/dpi \ --compiler clang \ -CFLAGS "-DTOPLEVEL_NAME=$(veril_top)" \ -CFLAGS "-DNR_LANES=$(nr_lanes)" \ -CFLAGS -I$(ROOT_DIR)/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp \ -CFLAGS -I$(ROOT_DIR)/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp \ -CFLAGS -I$(ROOT_DIR)/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp \ $(CLANG_CXXFLAGS) \ -LDFLAGS "-lelf" \ $(CLANG_LDFLAGS) \ --exe \ $(ROOT_DIR)/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/.cc \ $(ROOT_DIR)/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp/.cc \ $(ROOT_DIR)/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/*.cc \ $(ROOT_DIR)/tb/verilator/ara_tb.cpp \ --cc \ $(if $(trace),--trace-fst -Wno-INSECURE,) \ --top-module $(veril_top) && \ cd $(veril_library) && OBJCACHE='' make -j4 -f V$(veril_top).mk

Simulation

.PHONY: simv simv: $(veril_library)/V$(veril_top) $(if $(trace),-t,) -l ram,$(app_path)/$(app),elf

.PHONY: riscv_tests_simv riscv_tests_simv: $(tests)

$(tests): rv%: $(app_path)/rv% $(veril_library)/V$(veril_top) $(if $(trace),-t,) -l ram,$<,elf &> $(buildpath)/$@.trace

Lint

.PHONY: lint spyglass/tmp/files

SNPS_SG ?= spyglass-2022.06 lint: spyglass/tmp/files spyglass/sdc/func.sdc spyglass/scripts/run_lint.tcl cd spyglass; $(SNPS_SG) sg_shell -tcl scripts/run_lint.tcl

spyglass/tmp/files: $(bender) mkdir -p spyglass/tmp ./bender script verilator -t rtl -t spyglass -t cva6_test $(bender_defs) --define SPYGLASS > spyglass/tmp/files

DPIs

.PHONY: dpi dpi: $(buildpath)/$(dpi_library)/ara_dpi.so

$(buildpath)/$(dpi_library)/%.o: tb/dpi/%.cc mkdir -p $(buildpath)/$(dpi_library) $(CXX) -shared -fPIC -std=c++11 -Bsymbolic -c $< -I$(VERILATOR_INCLUDE) -I$(INSTALL_DIR)/riscv-isa-sim/include -o $@

$(buildpath)/$(dpi_library)/ara_dpi.so: $(dpi) mkdir -p $(buildpath)/$(dpi_library) $(CXX) -shared -m64 -o $(buildpath)/$(dpi_library)/ara_dpi.so $?

Clean targets

.PHONY: clean clean: rm -rf $(buildpath)

rm -f bender

takeshineshiro commented 1 year ago

also the content ofrtl_cmod.f is like below: +incdir+${ARA_ROOT}

${ARA_ROOT}/hardware/deps/tech_cells_generic/src/rtl/tc_sram.sv ${ARA_ROOT}/hardware/deps/tech_cells_generic/src/deprecated/cluster_clk_cells.sv ${ARA_ROOT}/hardware/deps/tech_cells_generic/src/deprecated/pulp_clk_cells.sv ${ARA_ROOT}/hardware/deps/tech_cells_generic/src/rtl/tc_clk.sv ${ARA_ROOT}/hardware/deps/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv

+incdir+${ARA_ROOT}/hardware/deps/common_cells +incdir+${ARA_ROOT}/hardware/deps/common_cells/include ${ARA_ROOT}/hardware/deps/common_cells/src/binary_to_gray.sv ${ARA_ROOT}/hardware/deps/common_cells/src/cb_filter_pkg.sv ${ARA_ROOT}/hardware/deps/common_cells/src/cdc_2phase.sv ${ARA_ROOT}/hardware/deps/common_cells/src/cf_math_pkg.sv ${ARA_ROOT}/hardware/deps/common_cells/src/clk_div.sv ${ARA_ROOT}/hardware/deps/common_cells/src/delta_counter.sv ${ARA_ROOT}/hardware/deps/common_cells/src/ecc_pkg.sv ${ARA_ROOT}/hardware/deps/common_cells/src/edge_propagator_tx.sv ${ARA_ROOT}/hardware/deps/common_cells/src/exp_backoff.sv ${ARA_ROOT}/hardware/deps/common_cells/src/fifo_v3.sv ${ARA_ROOT}/hardware/deps/common_cells/src/gray_to_binary.sv ${ARA_ROOT}/hardware/deps/common_cells/src/isochronous_spill_register.sv ${ARA_ROOT}/hardware/deps/common_cells/src/lfsr.sv ${ARA_ROOT}/hardware/deps/common_cells/src/lfsr_16bit.sv ${ARA_ROOT}/hardware/deps/common_cells/src/lfsr_8bit.sv ${ARA_ROOT}/hardware/deps/common_cells/src/mv_filter.sv ${ARA_ROOT}/hardware/deps/common_cells/src/onehot_to_bin.sv ${ARA_ROOT}/hardware/deps/common_cells/src/plru_tree.sv ${ARA_ROOT}/hardware/deps/common_cells/src/popcount.sv ${ARA_ROOT}/hardware/deps/common_cells/src/rr_arb_tree.sv ${ARA_ROOT}/hardware/deps/common_cells/src/rstgen_bypass.sv ${ARA_ROOT}/hardware/deps/common_cells/src/serial_deglitch.sv ${ARA_ROOT}/hardware/deps/common_cells/src/shift_reg.sv ${ARA_ROOT}/hardware/deps/common_cells/src/spill_register_flushable.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_demux.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_filter.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_fork.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_intf.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_join.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_mux.sv ${ARA_ROOT}/hardware/deps/common_cells/src/sub_per_hash.sv ${ARA_ROOT}/hardware/deps/common_cells/src/sync.sv ${ARA_ROOT}/hardware/deps/common_cells/src/sync_wedge.sv ${ARA_ROOT}/hardware/deps/common_cells/src/unread.sv ${ARA_ROOT}/hardware/deps/common_cells/src/addr_decode.sv ${ARA_ROOT}/hardware/deps/common_cells/src/cb_filter.sv ${ARA_ROOT}/hardware/deps/common_cells/src/cdc_fifo_2phase.sv ${ARA_ROOT}/hardware/deps/common_cells/src/counter.sv ${ARA_ROOT}/hardware/deps/common_cells/src/ecc_decode.sv ${ARA_ROOT}/hardware/deps/common_cells/src/ecc_encode.sv ${ARA_ROOT}/hardware/deps/common_cells/src/edge_detect.sv ${ARA_ROOT}/hardware/deps/common_cells/src/lzc.sv ${ARA_ROOT}/hardware/deps/common_cells/src/max_counter.sv ${ARA_ROOT}/hardware/deps/common_cells/src/rstgen.sv ${ARA_ROOT}/hardware/deps/common_cells/src/spill_register.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_delay.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_fifo.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_fork_dynamic.sv ${ARA_ROOT}/hardware/deps/common_cells/src/cdc_fifo_gray.sv ${ARA_ROOT}/hardware/deps/common_cells/src/fall_through_register.sv ${ARA_ROOT}/hardware/deps/common_cells/src/id_queue.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_to_mem.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_arbiter_flushable.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_register.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_xbar.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_arbiter.sv ${ARA_ROOT}/hardware/deps/common_cells/src/stream_omega_net.sv ${ARA_ROOT}/hardware/deps/common_cells/src/deprecated/clock_divider_counter.sv ${ARA_ROOT}/hardware/deps/common_cells/src/deprecated/find_first_one.sv ${ARA_ROOT}/hardware/deps/common_cells/src/deprecated/generic_LFSR_8bit.sv ${ARA_ROOT}/hardware/deps/common_cells/src/deprecated/generic_fifo.sv ${ARA_ROOT}/hardware/deps/common_cells/src/deprecated/prioarbiter.sv ${ARA_ROOT}/hardware/deps/common_cells/src/deprecated/pulp_sync.sv ${ARA_ROOT}/hardware/deps/common_cells/src/deprecated/pulp_sync_wedge.sv ${ARA_ROOT}/hardware/deps/common_cells/src/deprecated/rrarbiter.sv ${ARA_ROOT}/hardware/deps/common_cells/src/deprecated/clock_divider.sv ${ARA_ROOT}/hardware/deps/common_cells/src/deprecated/fifo_v2.sv ${ARA_ROOT}/hardware/deps/common_cells/src/deprecated/fifo_v1.sv ${ARA_ROOT}/hardware/deps/common_cells/src/edge_propagator.sv ${ARA_ROOT}/hardware/deps/common_cells/src/edge_propagator_rx.sv

+incdir+${ARA_ROOT}/hardware/deps/axi/include ${ARA_ROOT}/hardware/deps/axi/src/axi_pkg.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_intf.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_atop_filter.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_burst_splitter.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_cdc_dst.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_cdc_src.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_cut.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_delayer.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_demux.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_dw_downsizer.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_dw_upsizer.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_id_prepend.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_isolate.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_join.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_lite_demux.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_lite_join.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_lite_mailbox.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_lite_mux.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_lite_regs.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_lite_to_apb.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_lite_to_axi.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_modify_address.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_mux.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_serializer.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_cdc.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_err_slv.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_dw_converter.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_multicut.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_to_axi_lite.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_lite_xbar.sv ${ARA_ROOT}/hardware/deps/axi/src/axi_xbar.sv

+incdir+${ARA_ROOT}/hardware/deps/cva6/include ${ARA_ROOT}/hardware/deps/cva6/include/riscv_pkg.sv ${ARA_ROOT}/hardware/deps/cva6/src/riscv-dbg/src/dm_pkg.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpnew_pkg.sv ${ARA_ROOT}/hardware/deps/cva6/include/ariane_pkg.sv ${ARA_ROOT}/hardware/deps/cva6/include/std_cache_pkg.sv ${ARA_ROOT}/hardware/deps/cva6/include/wt_cache_pkg.sv ${ARA_ROOT}/hardware/deps/cva6/src/register_interface/src/reg_intf.sv ${ARA_ROOT}/hardware/deps/cva6/src/register_interface/src/reg_intf_pkg.sv ${ARA_ROOT}/hardware/deps/cva6/include/ariane_axi_pkg.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv ${ARA_ROOT}/hardware/deps/cva6/src/ariane.sv ${ARA_ROOT}/hardware/deps/cva6/src/serdiv.sv ${ARA_ROOT}/hardware/deps/cva6/src/ariane_regfile_ff.sv ${ARA_ROOT}/hardware/deps/cva6/src/amo_buffer.sv ${ARA_ROOT}/hardware/deps/cva6/src/id_stage.sv ${ARA_ROOT}/hardware/deps/cva6/src/branch_unit.sv ${ARA_ROOT}/hardware/deps/cva6/src/instr_realign.sv ${ARA_ROOT}/hardware/deps/cva6/src/load_store_unit.sv ${ARA_ROOT}/hardware/deps/cva6/src/controller.sv ${ARA_ROOT}/hardware/deps/cva6/src/issue_stage.sv ${ARA_ROOT}/hardware/deps/cva6/src/re_name.sv ${ARA_ROOT}/hardware/deps/cva6/src/csr_buffer.sv ${ARA_ROOT}/hardware/deps/cva6/src/tlb.sv ${ARA_ROOT}/hardware/deps/cva6/src/decoder.sv ${ARA_ROOT}/hardware/deps/cva6/src/scoreboard.sv ${ARA_ROOT}/hardware/deps/cva6/src/perf_counters.sv ${ARA_ROOT}/hardware/deps/cva6/src/store_unit.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_adapter.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu_wrap.sv ${ARA_ROOT}/hardware/deps/cva6/src/csr_regfile.sv ${ARA_ROOT}/hardware/deps/cva6/src/commit_stage.sv ${ARA_ROOT}/hardware/deps/cva6/src/alu.sv ${ARA_ROOT}/hardware/deps/cva6/src/multiplier.sv ${ARA_ROOT}/hardware/deps/cva6/src/store_buffer.sv ${ARA_ROOT}/hardware/deps/cva6/src/compressed_decoder.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_shim.sv ${ARA_ROOT}/hardware/deps/cva6/src/ex_stage.sv ${ARA_ROOT}/hardware/deps/cva6/src/mmu.sv ${ARA_ROOT}/hardware/deps/cva6/src/ptw.sv ${ARA_ROOT}/hardware/deps/cva6/src/mult.sv ${ARA_ROOT}/hardware/deps/cva6/src/load_unit.sv ${ARA_ROOT}/hardware/deps/cva6/src/issue_read_operands.sv ${ARA_ROOT}/hardware/deps/cva6/src/acc_dispatcher.sv ${ARA_ROOT}/hardware/deps/cva6/src/pmp/src/pmp_entry.sv ${ARA_ROOT}/hardware/deps/cva6/src/pmp/src/pmp.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpnew_fma.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpnew_opgroup_fmt_slice.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpnew_divsqrt_multi.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpnew_fma_multi.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpnew_opgroup_multifmt_slice.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpnew_classifier.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpnew_noncomp.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpnew_cast_multi.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpnew_opgroup_block.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpnew_rounding.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpnew_top.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv ${ARA_ROOT}/hardware/deps/cva6/src/frontend/frontend.sv ${ARA_ROOT}/hardware/deps/cva6/src/frontend/instr_scan.sv ${ARA_ROOT}/hardware/deps/cva6/src/frontend/instr_queue.sv ${ARA_ROOT}/hardware/deps/cva6/src/frontend/bht.sv ${ARA_ROOT}/hardware/deps/cva6/src/frontend/btb.sv ${ARA_ROOT}/hardware/deps/cva6/src/frontend/ras.sv ${ARA_ROOT}/hardware/deps/cva6/src/cache_subsystem/tag_cmp.sv ${ARA_ROOT}/hardware/deps/cva6/src/cache_subsystem/cache_ctrl.sv ${ARA_ROOT}/hardware/deps/cva6/src/cache_subsystem/amo_alu.sv ${ARA_ROOT}/hardware/deps/cva6/src/cache_subsystem/wt_axi_adapter.sv ${ARA_ROOT}/hardware/deps/cva6/src/cache_subsystem/wt_dcache_ctrl.sv ${ARA_ROOT}/hardware/deps/cva6/src/cache_subsystem/wt_cache_subsystem.sv ${ARA_ROOT}/hardware/deps/cva6/src/cache_subsystem/wt_dcache_missunit.sv ${ARA_ROOT}/hardware/deps/cva6/src/cache_subsystem/cva6_icache.sv ${ARA_ROOT}/hardware/deps/cva6/src/cache_subsystem/wt_dcache_wbuffer.sv ${ARA_ROOT}/hardware/deps/cva6/src/cache_subsystem/wt_l15_adapter.sv ${ARA_ROOT}/hardware/deps/cva6/src/cache_subsystem/wt_dcache_mem.sv ${ARA_ROOT}/hardware/deps/cva6/src/cache_subsystem/cva6_icache_axi_wrapper.sv ${ARA_ROOT}/hardware/deps/cva6/src/cache_subsystem/std_cache_subsystem.sv ${ARA_ROOT}/hardware/deps/cva6/src/cache_subsystem/wt_dcache.sv ${ARA_ROOT}/hardware/deps/cva6/src/clint/axi_lite_interface.sv ${ARA_ROOT}/hardware/deps/cva6/src/clint/clint.sv ${ARA_ROOT}/hardware/deps/cva6/fpga/src/axi2apb/src/axi2apb_wrap.sv ${ARA_ROOT}/hardware/deps/cva6/fpga/src/axi2apb/src/axi2apb.sv ${ARA_ROOT}/hardware/deps/cva6/fpga/src/axi2apb/src/axi2apb_64_32.sv ${ARA_ROOT}/hardware/deps/cva6/fpga/src/axi_slice/src/axi_w_buffer.sv ${ARA_ROOT}/hardware/deps/cva6/fpga/src/axi_slice/src/axi_b_buffer.sv ${ARA_ROOT}/hardware/deps/cva6/fpga/src/axi_slice/src/axi_slice_wrap.sv ${ARA_ROOT}/hardware/deps/cva6/fpga/src/axi_slice/src/axi_slice.sv ${ARA_ROOT}/hardware/deps/cva6/fpga/src/axi_slice/src/axi_single_slice.sv ${ARA_ROOT}/hardware/deps/cva6/fpga/src/axi_slice/src/axi_ar_buffer.sv ${ARA_ROOT}/hardware/deps/cva6/fpga/src/axi_slice/src/axi_r_buffer.sv ${ARA_ROOT}/hardware/deps/cva6/fpga/src/axi_slice/src/axi_aw_buffer.sv ${ARA_ROOT}/hardware/deps/cva6/fpga/src/apb_timer/apb_timer.sv ${ARA_ROOT}/hardware/deps/cva6/fpga/src/apb_timer/timer.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_regs_top.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_BR_allocator.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_BW_allocator.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_address_decoder_BR.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_DW_allocator.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_address_decoder_BW.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_address_decoder_DW.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_node_arbiter.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_response_block.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_request_block.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_AR_allocator.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_AW_allocator.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_address_decoder_AR.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_address_decoder_AW.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/apb_regs_top.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_node_intf_wrap.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_node.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_node_wrap_with_slices.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_node/src/axi_multiplexer.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_riscv_atomics/src/axi_riscv_amos.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_riscv_atomics/src/axi_riscv_atomics.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_riscv_atomics/src/axi_res_tbl.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv ${ARA_ROOT}/hardware/deps/cva6/src/axi_mem_if/src/axi2mem.sv ${ARA_ROOT}/hardware/deps/cva6/src/rv_plic/rtl/rv_plic_target.sv ${ARA_ROOT}/hardware/deps/cva6/src/rv_plic/rtl/rv_plic_gateway.sv ${ARA_ROOT}/hardware/deps/cva6/src/rv_plic/rtl/plic_regmap.sv ${ARA_ROOT}/hardware/deps/cva6/src/rv_plic/rtl/plic_top.sv ${ARA_ROOT}/hardware/deps/cva6/src/riscv-dbg/src/dmi_cdc.sv ${ARA_ROOT}/hardware/deps/cva6/src/riscv-dbg/src/dmi_jtag.sv ${ARA_ROOT}/hardware/deps/cva6/src/riscv-dbg/src/dmi_jtag_tap.sv ${ARA_ROOT}/hardware/deps/cva6/src/riscv-dbg/src/dm_csrs.sv ${ARA_ROOT}/hardware/deps/cva6/src/riscv-dbg/src/dm_mem.sv ${ARA_ROOT}/hardware/deps/cva6/src/riscv-dbg/src/dm_sba.sv ${ARA_ROOT}/hardware/deps/cva6/src/riscv-dbg/src/dm_top.sv ${ARA_ROOT}/hardware/deps/cva6/src/riscv-dbg/debug_rom/debug_rom.sv ${ARA_ROOT}/hardware/deps/cva6/src/register_interface/src/apb_to_reg.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/deprecated/generic_fifo.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/deprecated/pulp_sync.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/deprecated/find_first_one.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/rstgen_bypass.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/rstgen.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/stream_mux.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/stream_demux.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/stream_arbiter.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/stream_arbiter_flushable.sv ${ARA_ROOT}/hardware/deps/cva6/src/util/axi_master_connect.sv ${ARA_ROOT}/hardware/deps/cva6/src/util/axi_slave_connect.sv ${ARA_ROOT}/hardware/deps/cva6/src/util/axi_master_connect_rev.sv ${ARA_ROOT}/hardware/deps/cva6/src/util/axi_slave_connect_rev.sv ${ARA_ROOT}/hardware/deps/cva6/src/fpga-support/rtl/SyncSpRamBeNx64.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/popcount.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/unread.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/cdc_2phase.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/spill_register.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/edge_detect.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/fifo_v3.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/deprecated/fifo_v2.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/deprecated/fifo_v1.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/lzc.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/rr_arb_tree.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/deprecated/rrarbiter.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/stream_delay.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/lfsr.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/lfsr_8bit.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/lfsr_16bit.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/counter.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/shift_reg.sv ${ARA_ROOT}/hardware/deps/cva6/src/common_cells/src/exp_backoff.sv ${ARA_ROOT}/hardware/deps/cva6/src/tech_cells_generic/src/cluster_clock_inverter.sv ${ARA_ROOT}/hardware/deps/cva6/src/tech_cells_generic/src/pulp_clock_mux2.sv ${ARA_ROOT}/hardware/deps/cva6/tb/ariane_soc_pkg.sv ${ARA_ROOT}/hardware/deps/cva6/tb/ariane_axi_soc_pkg.sv ${ARA_ROOT}/hardware/deps/cva6/tb/ariane_testharness.sv ${ARA_ROOT}/hardware/deps/cva6/tb/ariane_peripherals.sv ${ARA_ROOT}/hardware/deps/cva6/tb/common/uart.sv ${ARA_ROOT}/hardware/deps/cva6/tb/common/SimDTM.sv ${ARA_ROOT}/hardware/deps/cva6/tb/common/SimJTAG.sv ${ARA_ROOT}/hardware/deps/cva6/bootrom/bootrom.sv ${ARA_ROOT}/hardware/deps/cva6/tb/common/mock_uart.sv ${ARA_ROOT}/hardware/deps/cva6/src/util/sram.sv ${ARA_ROOT}/hardware/include/rvv_pkg.sv ${ARA_ROOT}/hardware/include/ara_pkg.sv ${ARA_ROOT}/hardware/src/axi_to_mem.sv ${ARA_ROOT}/hardware/src/ctrl_registers.sv ${ARA_ROOT}/hardware/src/cva6_accel_first_pass_decoder.sv ${ARA_ROOT}/hardware/src/ara_dispatcher.sv ${ARA_ROOT}/hardware/src/ara_sequencer.sv ${ARA_ROOT}/hardware/src/axi_inval_filter.sv

+incdir+${ARA_ROOT}/hardware/include ${ARA_ROOT}/hardware/src/lane/lane_sequencer.sv ${ARA_ROOT}/hardware/src/lane/operand_queue.sv ${ARA_ROOT}/hardware/src/lane/operand_requester.sv ${ARA_ROOT}/hardware/src/lane/simd_alu.sv ${ARA_ROOT}/hardware/src/lane/simd_div.sv ${ARA_ROOT}/hardware/src/lane/simd_mul.sv ${ARA_ROOT}/hardware/src/lane/vector_regfile.sv ${ARA_ROOT}/hardware/src/masku/masku.sv ${ARA_ROOT}/hardware/src/sldu/sldu.sv ${ARA_ROOT}/hardware/src/vlsu/addrgen.sv ${ARA_ROOT}/hardware/src/vlsu/vldu.sv ${ARA_ROOT}/hardware/src/vlsu/vstu.sv ${ARA_ROOT}/hardware/src/lane/operand_queues_stage.sv ${ARA_ROOT}/hardware/src/lane/valu.sv ${ARA_ROOT}/hardware/src/lane/vmfpu.sv ${ARA_ROOT}/hardware/src/lane/fixed_p_rounding.sv ${ARA_ROOT}/hardware/src/vlsu/vlsu.sv ${ARA_ROOT}/hardware/src/lane/vector_fus_stage.sv ${ARA_ROOT}/hardware/src/lane/lane.sv ${ARA_ROOT}/hardware/src/ara.sv ${ARA_ROOT}/hardware/src/ara_system.sv ${ARA_ROOT}/hardware/src/ara_soc.sv ${ARA_ROOT}/hardware/tb/ara_testharness.sv ${ARA_ROOT}/hardware/tb/ara_tb.sv ${ARA_ROOT}/hardware/src/accel_dispatcher_ideal.sv ${ARA_ROOT}/hardware/tb/ara_tb_verilator.sv

+incdir+${ARA_ROOT}/hardware/deps/cva6/src/util +incdir+${ARA_ROOT}/hardware/deps/cva6/include ${ARA_ROOT}/hardware/deps/cva6/include/instr_tracer_pkg.sv ${ARA_ROOT}/hardware/deps/cva6/src/util/instr_tracer_if.sv ${ARA_ROOT}/hardware/deps/cva6/src/util/instr_tracer.sv

lczzz29 commented 1 year ago

@takeshineshiro hello may you update your modified makefile for VCS and share a file link (or as an attachment) plz? your above answers are unreadable because of the text format used in github issues (and maybe recognized as markdown syntax incorrectly). thx.