Tanishqgithub commented 2 months ago

Respected sir

I am working on Oracle virtual box with Ubuntu 22.04 LTS version

I ran the prerequisite dependency commands which gave some 404 error but was overcome using the --fix-missing
cloned the repository along with the submodules
make toolchain-llvm [abnormally there were some "failed" for tests when we run this] a. Is that ok ? b. i sense something wrong in my clang installation [please see "clang.png" , the path is not printed]
make riscv-isa-sim [no problem running it]
make verilator [no problem running it after running sudo apt-get install libstdc++-12-dev ]
tried running other "apps" other than hello_world like fmatmul and got o/p as in "fmatmul.txt" a. Why is the number of cycles 0 and performance is also not computed ? b. In this step is the application running on the vector processor designed only? because not integrated with CVA6 till now .. fmatmul.txt
make riscv_tests : a. solved after running make toolchain-gcc
from RTL Simulation of README : a. tried running make checkout but got the error message in "make_checkout.png" b. please guide from this step

mp-17 commented 2 months ago

Hello @Tanishqgithub,

Provided that you have already installed Verilator and run make -C hardware apply-patches once, please try to run the following commands and let me know what happens:

# Compile fmatmul for Ara
make -C apps bin/fmatmul
# Verilate the design
make -C hardware verilate
# Run fmatmul on Ara through Verilator
make -C hardware simv app=fmatmul

mp-17 commented 2 months ago

It seems that make checkout worked correctly. 1) Which shell are you using? Bash? 2) Can you please format the previous message? It's very hard to read. Please put the code within ``` delimiters. Example:

 code
 code
 code

Tanishqgithub commented 2 months ago

Note the prerequists command i ran which is there in [1. ] in previous message is :

sudo apt update
sudo apt-get install -y build-essential git doxygen python3-pip libsdl2-dev curl cmake gtkwave libsndfile1-dev rsync autoconf automake texinfo libtool pkg-config libsdl2-ttf-dev ninja-build

After running the make -C hardware apply-patches i got this o/p :

After running the command mentioned above i,e :

# Compile fmatmul for Ara
make -C app bin/fmatmul
# Verilate the design
make -C hardware verilate
# Run fmatmul on Ara through Verilator
make -C hardware simv app=fmatmul

i got the following o/p : error.txt

Note from the previous message i couldn't run the make checkout command which is the starting of RTL Simulation section of README .

If my command is working fine please tell me what are the next final commands after this step of command and why is there in finding the QuestaSim Version and the deps : No such file or directory

Yes i am using the bash shell

mp-17 commented 2 months ago

make checkout is working correctly. The messages about QuestaSim and find are acceptable. The patches have also been applied correctly.

For the compilation, there was a typo in my command, sorry. You should first give:

make -C apps bin/fmatmul

Then, it seems you also have a problem with Verilator.

sh: 1: exec: /home/tanishq/Documents/ARAnew/ara/install/verilator/share/verilator/verilator_bin: not found
%Error: Command Failed ulimit -s unlimited 2>/dev/null; exec /home/tanishq/Documents/ARAnew/ara/install/verilator/share/verilator/verilator_bin -f

I am not sure why you get this. You can first try to re-install a fresh version of Verilator and check that you have not got any errors while installing it. Before installing it, be sure that VERILATOR_ROOT is clean with unset VERILATOR_ROOT.

If the issue is not solved, you can ask for support in the Verilator repository.

Otherwise, if you can access QuestaSim, you can simulate with it by replacing simv with simc when you issue the make command.

Tanishqgithub commented 2 months ago

As per your suggestion i tried out to re-install verilator using the command make -B verilator after cleaning the path VERILATOR_ROOT I got this log file : verilator.txt As per the log the verilator is successfully installed

but after i run

# Compile fmatmul for Ara
make -C apps bin/fmatmul
# Verilate the design
make -C hardware verilate
# Run fmatmul on Ara through Verilator
make -C hardware simv app=fmatmul

i got the following o/p which is same as previous situation :

tanishq@Tanishq:~/Documents/ARAnew/ara$ # Compile fmatmul for Ara

make -C apps bin/fmatmul

# Verilate the design

make -C hardware verilate

# Run fmatmul on Ara through Verilator

make -C hardware simv app=fmatmul

make: Entering directory '/home/tanishq/Documents/ARAnew/ara/apps'

cd fmatmul && if [ -d script ]; then python3 script/gen_data.py 128 128 128 > data.S ; else touch data.S; fi

/home/tanishq/Documents/ARAnew/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARAnew/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf  -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument  -ffunction-sections -fdata-sections -c fmatmul/data.S -o fmatmul/data.S.o

chmod +x /home/tanishq/Documents/ARAnew/ara/apps/common/script/align_sections.sh

rm -f /home/tanishq/Documents/ARAnew/ara/apps/common/link.ld && cp /home/tanishq/Documents/ARAnew/ara/apps/common/arch.link.ld /home/tanishq/Documents/ARAnew/ara/apps/common/link.ld

/home/tanishq/Documents/ARAnew/ara/apps/common/script/align_sections.sh 4 /home/tanishq/Documents/ARAnew/ara/apps/common/link.ld

/home/tanishq/Documents/ARAnew/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARAnew/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf  -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument  -ffunction-sections -fdata-sections -c fmatmul/main.c -o fmatmul/main.c.o

/home/tanishq/Documents/ARAnew/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARAnew/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf  -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument  -ffunction-sections -fdata-sections -c common/crt0.S -o common/crt0-llvm.S.o

/home/tanishq/Documents/ARAnew/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARAnew/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf  -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument  -ffunction-sections -fdata-sections -c common/printf.c -o common/printf-llvm.c.o

/home/tanishq/Documents/ARAnew/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARAnew/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf  -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument  -ffunction-sections -fdata-sections -c common/string.c -o common/string-llvm.c.o

/home/tanishq/Documents/ARAnew/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARAnew/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf  -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument  -ffunction-sections -fdata-sections -c common/serial.c -o common/serial-llvm.c.o

/home/tanishq/Documents/ARAnew/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARAnew/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf  -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument  -ffunction-sections -fdata-sections -c common/util.c -o common/util-llvm.c.o

mkdir -p bin/

/home/tanishq/Documents/ARAnew/ara/install/riscv-llvm/bin/clang -Iinclude -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARAnew/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf  -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument  -ffunction-sections -fdata-sections -o bin/fmatmul fmatmul/kernel/fmatmul.c.o fmatmul/main.c.o fmatmul/data.S.o common/crt0-llvm.S.o common/printf-llvm.c.o common/string-llvm.c.o common/serial-llvm.c.o common/util-llvm.c.o -static -nostartfiles -lm -Wl,--gc-sections -T/home/tanishq/Documents/ARAnew/ara/apps/common/link.ld

ld.lld: warning: ignoring memory region assignment for non-allocatable section '.comment'

/home/tanishq/Documents/ARAnew/ara/install/riscv-llvm/bin/llvm-objdump --mattr=v -D bin/fmatmul > bin/fmatmul.dump

/home/tanishq/Documents/ARAnew/ara/install/riscv-llvm/bin/llvm-strip bin/fmatmul -S --strip-unneeded

rm common/serial-llvm.c.o common/printf-llvm.c.o common/crt0-llvm.S.o common/util-llvm.c.o common/string-llvm.c.o fmatmul/main.c.o

make: Leaving directory '/home/tanishq/Documents/ARAnew/ara/apps'

make: Entering directory '/home/tanishq/Documents/ARAnew/ara/hardware'

Makefile:83: "Specified QuestaSim version (questa-2021.2) not found in PATH /home/tanishq/.local/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin"

rm -rf build/verilator; mkdir -p build/verilator

/home/tanishq/Documents/ARAnew/ara/hardware/../hardware/bender script verilator -t rtl -t cv64a6_imafdcv_sv39 -t tech_cells_generic_include_tc_sram -t tech_cells_generic_include_tc_clk -t ara_test -t cva6_test -t verilator --define NR_LANES=4 --define VLEN=4096 --define ARIANE_ACCELERATOR_PORT=1 --define COMMON_CELLS_ASSERTS_OFF > build/verilator/bender_script_default

/home/tanishq/Documents/ARAnew/ara/install/verilator/bin/verilator -f build/verilator/bender_script_default           \

  -GNrLanes=4                                                         \

  -O3                                                                           \

  -Wno-fatal                                                                    \

  -Wno-PINCONNECTEMPTY                                                          \

  -Wno-BLKANDNBLK                                                               \

  -Wno-CASEINCOMPLETE                                                           \

  -Wno-CMPCONST                                                                 \

  -Wno-LATCH                                                                    \

  -Wno-LITENDIAN                                                                \

  -Wno-UNOPTFLAT                                                                \

  -Wno-UNPACKED                                                                 \

  -Wno-UNSIGNED                                                                 \

  -Wno-WIDTH                                                                    \

  -Wno-WIDTHCONCAT                                                              \

  -Wno-ENUMVALUE                                                                \

  -Wno-COMBDLY                                                                  \

  --hierarchical                                                                \

  tb/verilator/waiver.vlt                                                       \

  --Mdir build/verilator                                                       \

  -Itb/dpi                                                                      \

  --compiler clang                                                              \

  -CFLAGS "-DTOPLEVEL_NAME=ara_tb_verilator"                                        \

  -CFLAGS "-DNR_LANES=4"                                              \

  -CFLAGS -I/home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp       \

  -CFLAGS -I/home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp \

  -CFLAGS -I/home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp \

  ""                                                             \

  -LDFLAGS "-lelf"                                                              \

  ""                                                              \

  --exe                                                                         \

  /home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/*.cc            \

  /home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp/*.cc      \

  /home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/*.cc      \

  /home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/ara_tb.cpp                                           \

  --cc                                                                          \

                                       \

  --top-module ara_tb_verilator &&                                                  \

cd build/verilator && OBJCACHE='' make -j4 -f Vara_tb_verilator.mk

make[1]: Entering directory '/home/tanishq/Documents/ARAnew/ara/hardware/build/verilator'

make[2]: Entering directory '/home/tanishq/Documents/ARAnew/ara/hardware'

/home/tanishq/Documents/ARAnew/ara/install/verilator/bin/verilator -f build/verilator/Vlane_e_hierMkArgs.f

sh: 1: exec: /home/tanishq/Documents/ARAnew/ara/install/verilator/share/verilator/verilator_bin: not found

%Error: Command Failed ulimit -s unlimited 2>/dev/null; exec /home/tanishq/Documents/ARAnew/ara/install/verilator/share/verilator/verilator_bin -f build/verilator/Vlane_e_hierMkArgs.f

make[2]: *** [build/verilator/Vara_tb_verilator_hier.mk:332: hier_launch_verilator] Error 127

make[2]: Leaving directory '/home/tanishq/Documents/ARAnew/ara/hardware'

make[1]: *** [Vara_tb_verilator_hier.mk:341: Vlane_e/lane_e.sv] Error 2

make[1]: Leaving directory '/home/tanishq/Documents/ARAnew/ara/hardware/build/verilator'

%Error: make -C build/verilator -f Vara_tb_verilator_hier.mk  -j 1  hier_verilation exited with 2

%Error: Command Failed ulimit -s unlimited 2>/dev/null; exec /home/tanishq/Documents/ARAnew/ara/install/verilator/bin/verilator_bin -f build/verilator/bender_script_default -GNrLanes=4 -O3 -Wno-fatal -Wno-PINCONNECTEMPTY -Wno-BLKANDNBLK -Wno-CASEINCOMPLETE -Wno-CMPCONST -Wno-LATCH -Wno-LITENDIAN -Wno-UNOPTFLAT -Wno-UNPACKED -Wno-UNSIGNED -Wno-WIDTH -Wno-WIDTHCONCAT -Wno-ENUMVALUE -Wno-COMBDLY --hierarchical tb/verilator/waiver.vlt --Mdir build/verilator -Itb/dpi --compiler clang -CFLAGS -DTOPLEVEL_NAME=ara_tb_verilator -CFLAGS -DNR_LANES=4 -CFLAGS -I/home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp -CFLAGS -I/home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp -CFLAGS -I/home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp  -LDFLAGS -lelf  --exe /home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/dpi_memutil.cc /home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/sv_scoped.cc /home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp/verilator_memutil.cc /home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilated_toplevel.cc /home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilator_sim_ctrl.cc /home/tanishq/Documents/ARAnew/ara/hardware/tb/verilator/ara_tb.cpp --cc --top-module ara_tb_verilator

make: *** [Makefile:188: build/verilator/Vara_tb_verilator] Error 2

make: Leaving directory '/home/tanishq/Documents/ARAnew/ara/hardware'

make: Entering directory '/home/tanishq/Documents/ARAnew/ara/hardware'

Makefile:83: "Specified QuestaSim version (questa-2021.2) not found in PATH /home/tanishq/.local/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin"

build/verilator/Vara_tb_verilator  -l ram,/home/tanishq/Documents/ARAnew/ara/apps/bin/fmatmul,elf

bash: line 1: build/verilator/Vara_tb_verilator: No such file or directory

make: *** [Makefile:232: simv] Error 127

make: Leaving directory '/home/tanishq/Documents/ARAnew/ara/hardware'

Can you please help me solving this issue and this time i didn't run make -C hardware apply-patches because the last time i used ARA i had executed it , is that correct ?

mp-17 commented 2 months ago

Yes, you can skip make -C hardware apply-patches if it has already been executed.

For Verilator, this seems the "interesting" error:

sh: 1: exec: /home/tanishq/Documents/ARAnew/ara/install/verilator/share/verilator/verilator_bin: not found

There is something problematic with your verilator setup.

Try attaching the .log from when you installed verilator with make verilator. Also, what is the output of: echo $VERILATOR_ROOT?

Ideally, VERILATOR_ROOT should be unset (i.e., unset VERILATOR_ROOT).

Tanishqgithub commented 2 months ago

when i run echo VERILATOR_ROOT i got the following output :
the config.log file is attached here : config.log

mp-17 commented 2 months ago

@Tanishqgithub,

My typo. The command should be: echo $VERILATOR_ROOT.

Do you have the full log of the make command when you issue make verilator to install Verilator?

Tanishqgithub commented 2 months ago

Oh yeah i also didn't notice that The output is attached below There is something definitely problem with the installation
I got the similar blank output for clang also so is this causing the problem ?
regarding the .log file , the log file which is attached in the previous message is the only log file which is present in directory /home/tanishq/Documents/ARAnew/ara/toolchain/verilator/ which is config.log above If that is not the complete log file , please tell me where i can find the complete log file for make verilator

mp-17 commented 2 months ago

1. That seems okay.

2. This is also okay. If you want to access the clang you installed with the make toolchains command, you can go into the ara directory and execute:

./install/riscv-llvm/bin/clang --version

3. When you install verilator from scratch, you can do:

make verilator |& tee verilator_install.log

Or, if you don't have tee:

make verilator &> verilator_install.log

Tanishqgithub commented 2 months ago

Respected sir

I re-clonned the entire setup and tried to start from first :

after running make toolchain-llvm &> toolchain_llvm_install.log i got this log file : toolchain_llvm_install.txt
after running make riscv-isa-sim &> riscv_isa_sim_install.log i got this log file : riscv_isa_sim_install.txt
after running make verilator &> verilator_install.log i got this log file : verilator_install.txt
Before running this :
```
cd apps
make riscv_tests
```
i ran this command make toolchain-gcc &> toolchain_gcc_install.log and got this log file : toolchain_gcc_install.txt

But i got the same o/p which is shown above in previous messages after running :

# Compile fmatmul for Ara
make -C apps bin/fmatmul
# Verilate the design
make -C hardware verilate
# Run fmatmul on Ara through Verilator
make -C hardware simv app=fmatmul

O/p :


tanishq@Tanishq:~/Documents/ARA_new/ara$ # Compile fmatmul for Ara

make -C apps bin/fmatmul

Verilate the design

make -C hardware verilate

Run fmatmul on Ara through Verilator

make -C hardware simv app=fmatmul

make: Entering directory '/home/tanishq/Documents/ARA_new/ara/apps'

cd fmatmul && if [ -d script ]; then python3 script/gen_data.py 128 128 128 > data.S ; else touch data.S; fi

/home/tanishq/Documents/ARA_new/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARA_new/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -ffunction-sections -fdata-sections -c fmatmul/data.S -o fmatmul/data.S.o

/home/tanishq/Documents/ARA_new/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARA_new/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -ffunction-sections -fdata-sections -c fmatmul/kernel/fmatmul.c -o fmatmul/kernel/fmatmul.c.o

chmod +x /home/tanishq/Documents/ARA_new/ara/apps/common/script/align_sections.sh

rm -f /home/tanishq/Documents/ARA_new/ara/apps/common/link.ld && cp /home/tanishq/Documents/ARA_new/ara/apps/common/arch.link.ld /home/tanishq/Documents/ARA_new/ara/apps/common/link.ld

/home/tanishq/Documents/ARA_new/ara/apps/common/script/align_sections.sh 4 /home/tanishq/Documents/ARA_new/ara/apps/common/link.ld

/home/tanishq/Documents/ARA_new/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARA_new/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -ffunction-sections -fdata-sections -c fmatmul/main.c -o fmatmul/main.c.o

/home/tanishq/Documents/ARA_new/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARA_new/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -ffunction-sections -fdata-sections -c common/crt0.S -o common/crt0-llvm.S.o

/home/tanishq/Documents/ARA_new/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARA_new/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -ffunction-sections -fdata-sections -c common/printf.c -o common/printf-llvm.c.o

/home/tanishq/Documents/ARA_new/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARA_new/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -ffunction-sections -fdata-sections -c common/string.c -o common/string-llvm.c.o

/home/tanishq/Documents/ARA_new/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARA_new/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -ffunction-sections -fdata-sections -c common/serial.c -o common/serial-llvm.c.o

/home/tanishq/Documents/ARA_new/ara/install/riscv-llvm/bin/clang -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARA_new/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -ffunction-sections -fdata-sections -c common/util.c -o common/util-llvm.c.o

mkdir -p bin/

/home/tanishq/Documents/ARA_new/ara/install/riscv-llvm/bin/clang -Iinclude -march=rv64gcv_zfh_zvfh0p1 -menable-experimental-extensions -mabi=lp64d -mno-relax -fuse-ld=lld -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -Xclang -target-feature -Xclang +no-optimized-zero-stride-load -mcmodel=medany -I/home/tanishq/Documents/ARA_new/ara/apps/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf -DNR_LANES=4 -DVLEN=4096 -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument -ffunction-sections -fdata-sections -o bin/fmatmul fmatmul/kernel/fmatmul.c.o fmatmul/main.c.o fmatmul/data.S.o common/crt0-llvm.S.o common/printf-llvm.c.o common/string-llvm.c.o common/serial-llvm.c.o common/util-llvm.c.o -static -nostartfiles -lm -Wl,--gc-sections -T/home/tanishq/Documents/ARA_new/ara/apps/common/link.ld

ld.lld: warning: ignoring memory region assignment for non-allocatable section '.comment'

/home/tanishq/Documents/ARA_new/ara/install/riscv-llvm/bin/llvm-objdump --mattr=v -D bin/fmatmul > bin/fmatmul.dump

/home/tanishq/Documents/ARA_new/ara/install/riscv-llvm/bin/llvm-strip bin/fmatmul -S --strip-unneeded

rm common/serial-llvm.c.o common/printf-llvm.c.o common/crt0-llvm.S.o common/util-llvm.c.o common/string-llvm.c.o fmatmul/main.c.o

make: Leaving directory '/home/tanishq/Documents/ARA_new/ara/apps'

make: Entering directory '/home/tanishq/Documents/ARA_new/ara/hardware'

Makefile:83: "Specified QuestaSim version (questa-2021.2) not found in PATH /home/tanishq/.local/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin"

mkdir -p build

rm -rf build/verilator; mkdir -p build/verilator

/home/tanishq/Documents/ARA_new/ara/hardware/../hardware/bender script verilator -t rtl -t cv64a6_imafdcv_sv39 -t tech_cells_generic_include_tc_sram -t tech_cells_generic_include_tc_clk -t ara_test -t cva6_test -t verilator --define NR_LANES=4 --define VLEN=4096 --define ARIANE_ACCELERATOR_PORT=1 --define COMMON_CELLS_ASSERTS_OFF > build/verilator/bender_script_default

/home/tanishq/Documents/ARA_new/ara/install/verilator/bin/verilator -f build/verilator/bender_script_default \

-GNrLanes=4 \

-O3 \

-Wno-fatal \

-Wno-PINCONNECTEMPTY \

-Wno-BLKANDNBLK \

-Wno-CASEINCOMPLETE \

-Wno-CMPCONST \

-Wno-LATCH \

-Wno-LITENDIAN \

-Wno-UNOPTFLAT \

-Wno-UNPACKED \

-Wno-UNSIGNED \

-Wno-WIDTH \

-Wno-WIDTHCONCAT \

-Wno-ENUMVALUE \

-Wno-COMBDLY \

--hierarchical \

tb/verilator/waiver.vlt \

--Mdir build/verilator \

-Itb/dpi \

--compiler clang \

-CFLAGS "-DTOPLEVEL_NAME=ara_tb_verilator" \

-CFLAGS "-DNR_LANES=4" \

-CFLAGS -I/home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp \

-CFLAGS -I/home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp \

-CFLAGS -I/home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp \

"" \

-LDFLAGS "-lelf" \

"" \

--exe \

/home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/*.cc \

/home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp/*.cc \

/home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/*.cc \

/home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/ara_tb.cpp \

--cc \

--top-module ara_tb_verilator && \

cd build/verilator && OBJCACHE='' make -j4 -f Vara_tb_verilator.mk

make[1]: Entering directory '/home/tanishq/Documents/ARA_new/ara/hardware/build/verilator'

make[2]: Entering directory '/home/tanishq/Documents/ARA_new/ara/hardware'

/home/tanishq/Documents/ARA_new/ara/install/verilator/bin/verilator -f build/verilator/Vlane_e_hierMkArgs.f

sh: 1: exec: /home/tanishq/Documents/ARA_new/ara/install/verilator/share/verilator/verilator_bin: not found

%Error: Command Failed ulimit -s unlimited 2>/dev/null; exec /home/tanishq/Documents/ARA_new/ara/install/verilator/share/verilator/verilator_bin -f build/verilator/Vlane_e_hierMkArgs.f

make[2]: *** [build/verilator/Vara_tb_verilator_hier.mk:332: hier_launch_verilator] Error 127

make[2]: Leaving directory '/home/tanishq/Documents/ARA_new/ara/hardware'

make[1]: *** [Vara_tb_verilator_hier.mk:341: Vlane_e/lane_e.sv] Error 2

make[1]: Leaving directory '/home/tanishq/Documents/ARA_new/ara/hardware/build/verilator'

%Error: make -C build/verilator -f Vara_tb_verilator_hier.mk -j 1 hier_verilation exited with 2

%Error: Command Failed ulimit -s unlimited 2>/dev/null; exec /home/tanishq/Documents/ARA_new/ara/install/verilator/bin/verilator_bin -f build/verilator/bender_script_default -GNrLanes=4 -O3 -Wno-fatal -Wno-PINCONNECTEMPTY -Wno-BLKANDNBLK -Wno-CASEINCOMPLETE -Wno-CMPCONST -Wno-LATCH -Wno-LITENDIAN -Wno-UNOPTFLAT -Wno-UNPACKED -Wno-UNSIGNED -Wno-WIDTH -Wno-WIDTHCONCAT -Wno-ENUMVALUE -Wno-COMBDLY --hierarchical tb/verilator/waiver.vlt --Mdir build/verilator -Itb/dpi --compiler clang -CFLAGS -DTOPLEVEL_NAME=ara_tb_verilator -CFLAGS -DNR_LANES=4 -CFLAGS -I/home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp -CFLAGS -I/home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp -CFLAGS -I/home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp -LDFLAGS -lelf --exe /home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/dpi_memutil.cc /home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp/sv_scoped.cc /home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp/verilator_memutil.cc /home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilated_toplevel.cc /home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp/verilator_sim_ctrl.cc /home/tanishq/Documents/ARA_new/ara/hardware/tb/verilator/ara_tb.cpp --cc --top-module ara_tb_verilator

make: *** [Makefile:188: build/verilator/Vara_tb_verilator] Error 2

make: Leaving directory '/home/tanishq/Documents/ARA_new/ara/hardware'

make: Entering directory '/home/tanishq/Documents/ARA_new/ara/hardware'

Makefile:83: "Specified QuestaSim version (questa-2021.2) not found in PATH /home/tanishq/.local/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin"

build/verilator/Vara_tb_verilator -l ram,/home/tanishq/Documents/ARA_new/ara/apps/bin/fmatmul,elf

bash: line 1: build/verilator/Vara_tb_verilator: No such file or directory

make: *** [Makefile:232: simv] Error 127

make: Leaving directory '/home/tanishq/Documents/ARA_new/ara/hardware'

tanishq@Tanishq:~/Documents/ARA_new/ara$



6. is the procedure of commands given correct regarding setup of toolchain ? or is there any other commands or
prerequisite needed ?

7. And i created Issue in [Verilator_github](https://github.com/verilator/verilator/issues/5209) and they replied saying that there is no issue with verilator rather issue with verilator installation [which is quite true]

8. And there is another method where we can simulate using QuestaSim , can you please share some insights in installing it and then commands to simulate using this .

mp-17 commented 2 months ago

Does the following command work? /home/tanishq/Documents/ARAnew/ara/install/verilator/bin/verilator --version

7. The problem remains the Verilator installation, but I don't see errors in the log and unluckily I don't know why the executable is searched in: /home/tanishq/Documents/ARA_new/ara/install/verilator/share/verilator/verilator_bin

You can try to patch the reference this way, but I don't think it will work:

mkdir -p /home/tanishq/Documents/ARA_new/ara/install/verilator/share/verilator
ln -s /home/tanishq/Documents/ARA_new/ara/install/verilator/bin/verilator_bin /home/tanishq/Documents/ARA_new/ara/install/verilator/share/verilator/verilator_bin

8. You need a license to use QuestaSim; if you have not one, you need to use Verilator

Tanishqgithub commented 2 months ago

Yes that command works :
The command you gave to patch was an excellent idea and actually solved the problem but gave to another error :
```
tanishq@Tanishq:~/Documents/ARA_new/ara$ # Compile fmatmul for Ara
```