Non-Compiler based test environment

[Tanishqgithub]

Respected Sir

I am trying to take the necessary design files and the testbench files [sv files] to run on Xilinx Vivado , but couldn't map onto which are all the files typically needed.

I am requesting you help me in identifying necessary files for ARA such that i have ARA_design.sv and the ARA_testbech.sv separately so that i can import these files in Vivado and execute these and analyze the waveform along with the power reports also.

I think the design phase starts from this basic step itself i just need that files which are used to simulate the ARA processor alone along with the testbench which provides the i/p Assembly level instructions [ISA] to the processor in each consecutive cycles.

For example : Same as we did to simulate the RISCV single cycle processor in https://github.com/Fede997/RISCV-PROCESSOR/blob/master/cpuRISCV-cpu_factorial.v :

Here the factorial.dat is the file where the Assembly level instructions are given in hexadecimal format to RISCV_CPU

mentioned here :

I know that the design phase starts with this type of file orientations so can u please share that files so that i can easily execute the sv files in vivado ?

Thanking You

[mp-17]

Hey @Tanishqgithub,

I probably did not get your question. The files needed for the testbench in hardware/tb while the source files are in hardware/deps (after make -C hardware checkout is run) and hardware/src. If you want to create a new testbench or environment for your FPGA, you will probably need an environment similar to what you have in ara_soc.sv, with a main memory in which you can load your program.