Closed andreaskuster closed 2 years ago
Timing analysis showed that the critical path is from the axi slave to the config and status register. This PR breaks this path with a spill register (we do not really care about an extra cycle on the config bus)
Timing analysis showed that the critical path is from the axi slave to the config and status register. This PR breaks this path with a spill register (we do not really care about an extra cycle on the config bus)