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pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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axi_lite_xbar component arbitration #2

Closed bchetwynd closed 6 years ago

bchetwynd commented 6 years ago

I am leveraging the axi_lite_xbar component to interface a hardware architecture processor to a variety of peripherals. As I am not terribly concerned with performance, I set it up to have two masters: instruction bus and data bus. Unfortunately, while the axi_lite_xbar has arbiters in it, reads and writes are separated. When I have the instruction bus (master 0) doing lots of reads, and the data bus (master 1) try to do a write, it seems to be permanently stalled. Is it possible to arbitrate reads and writes across all masters?

bchetwynd commented 6 years ago

Since Github won't let you delete issues, I merely need to close it. There is an issue with my peripheral... not the crossbar.

zarubaf commented 6 years ago

Okay, still happy to help if you run into troubles.

bchetwynd commented 6 years ago

Florian,

Much appreciated. I will say that after exploring things a bit more, it seems like the arbiter should arbitrate between read and write requests. Otherwise, I have can have concurrent requests going to a single component. I need to dig into the AXI4-Lite spec some more,, but I am guessing that concurrent operating the read and write channels is probably not allowed….

Thank you,

Brendon

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Brendon Chetwynd Technical Staff

MIT Lincoln Laboratory 

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From: Florian Zaruba notifications@github.com Sent: Wednesday, October 17, 2018 3:29 PM To: pulp-platform/axi axi@noreply.github.com Cc: Chetwynd, Brendon - 0551 - MITLL Brendon.Chetwynd@ll.mit.edu; State change state_change@noreply.github.com Subject: Re: [pulp-platform/axi] axi_lite_xbar component arbitration (#2)

Okay, still happy to help if you run into troubles.

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