Support Xilinx Vivado Simulator

[skokvermon]

Hi

I tried to simulate few axi benchs using xilinx vivado simulator. I could parse all the code with xvlog succesfuly But during elaboration I get errors like:

$ xelab tb_axi_dw_downsizer
Vivado Simulator v2021.2
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
Running: /home/skok/tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab tb_axi_dw_downsizer 
Multi-threading is on. Using 6 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
ERROR: [VRFC 10-2991] 'randomize' is not declared under prefix 'w_beat' [/home/skok/src/axi/src/axi_test.sv:1196]
ERROR: [VRFC 10-2991] 'randomize' is not declared under prefix 'r_beat' [/home/skok/src/axi/src/axi_test.sv:1335]
ERROR: [VRFC 10-2991] 'randomize' is not declared under prefix 'b_beat' [/home/skok/src/axi/src/axi_test.sv:1387]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'req_i' [/home/skok/src/axi/src/axi_dw_downsizer.sv:146]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'gnt_o' [/home/skok/src/axi/src/axi_dw_downsizer.sv:147]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

for another bench, there is a feature missing:

$ xelab tb_axi_delayer
Vivado Simulator v2021.2
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
Running: /home/skok/tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab tb_axi_delayer 
Multi-threading is on. Using 6 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
ERROR: [XSIM 43-3980] File "/home/skok/src/axi/src/axi_test.sv" Line 865 : The SystemVerilog feature "implication operator" is not supported yet for simulation.

xilinx vivado simulator may not implement all systemverilog features, but it is free. And it works under linux and windows. Supporting it could be nice.

[andreaskurth]

Thanks for your feedback, @skokvermon!

Supporting Xilinx Vivado Simulator would be desirable. Given the state of SystemVerilog support in the current Vivado Simulator (you tried v2021.2), however, this seems to require a lot of work. The simulation-only features of SystemVerilog are more complex than the synthesizable subset, and consequentially the divergence between EDA tools is even larger. That said, we are happy to get PRs that improve compatibility with Vivado while not breaking compatibility with other major simulators or making the code unreadable.

Concerning the errors you reported:

ERROR: [VRFC 10-2991] 'randomize' is not declared under prefix 'w_beat' [/home/skok/src/axi/src/axi_test.sv:1196]
ERROR: [VRFC 10-2991] 'randomize' is not declared under prefix 'r_beat' [/home/skok/src/axi/src/axi_test.sv:1335]
ERROR: [VRFC 10-2991] 'randomize' is not declared under prefix 'b_beat' [/home/skok/src/axi/src/axi_test.sv:1387]

The randomize() object method, which is built-in SystemVerilog for every class, randomizes the member variables of the object [IEEE Std 1800-2012, Sec. 18.6.1]. It is the correct way to randomize the member variables of a class object, whereas std::randomize() is used to randomize variables in the current scope [IEEE Std 1800-2012, Sec. 18.12]. While I am not aware that SystemVerilog standard explicitly allows or forbids the use of std::randomize() to randomize member variables, using std::randomize() on class objects is unsupported by at least one major simulator. Thus, I don't know a solution for this limitation of Vivado Simulator.

---

ERROR: [XSIM 43-3980] File "/home/skok/src/axi/src/axi_test.sv" Line 865 : The SystemVerilog feature "implication operator" is not supported yet for simulation.

The code referenced is a logical implication inside an assertion, and not a randomization constraint. Fixing this should be as simple as changing the line to

if (ax_beat.ax_burst == BURST_WRAP) assert(len inside {len_t'(1), len_t'(3), len_t'(7), len_t'(15)});

Could you try that and let us know if it solves your problem?

[skokvermon]

I could manage to remove all errors. But I now get a segfault during elaboration. I'm using fusesoc, which is very convenient for exporting designs. Design was uploaded to xilinx support forum https://support.xilinx.com/s/question/0D52E000076r7MUSAY/segfault-in-xelab-with-systemverilog-design

[andreaskurth]

Interesting, thanks for sharing! A diff of the design you uploaded to the current code shows that relatively few changes seem to be required. I will go through the changes and see if we can integrate them.

Since you mentioned FuseSoC, could you share the commands and configuration you used? I would be interested to integrate it into our CI flow (maybe even together with Vivado Simulator, once that works).

[skokvermon]

I will make pull requests. There 3 pull requests in common_cells, common_verification and axi However one of the changes is that vivado doesn't support empty() method and rand_id_queue in common_verification. The workaround is to change the method name from empty to is_empty This implies an interface change in all designs that use this. What I did is have both empty and is_empty defined

[andreaskurth]

I will make pull requests.

Perfect, thanks!

However one of the changes is that vivado doesn't support empty() method and rand_id_queue in common_verification. The workaround is to change the method name from empty to is_empty This implies an interface change in all designs that use this. What I did is have both empty and is_empty defined

That sounds reasonable. Defining both empty() and is_empty() means the interface does not break, as existing designs can keep using empty(). You could even put the definition of is_empty() inside an `ifdef XILINX_SIMULATOR to clarify that this is a Vivado-only workaround and not the preferred function.

[skokvermon]

I commited everything you can try by yourself. First install fusesoc, then:

mkdir fusesoc
cd fusesoc
fusesoc library add axi git@github.com:skokvermon/axi.git
fusesoc library add common_cells git@github.com:skokvermon/common_cells.git
fusesoc library add common_verification git@github.com:skokvermon/common_verification.git
fusesoc core list
fusesoc run --tool xsim --target sim --no-export pulp-platform.org::axi:0.35.2.dev

it will run simulation using vivado. Just change tool to whatever and it should work Note that I commited bench for tb_axi_dw_downsizer which has anoth problem I don't know how to solve, related to call to new's superclass. Seems like another bug in xsim

If you want to change the toplevel bench, just edit fusesoc_libraries/axi/axi.core and change at the bottom the name of the bench to tb_axi_cdc for example. this one segfaults for me.

[skokvermon]

Hi, have you tried? Do you want me to make pull requests?

[andreaskurth]

Do you want me to make pull requests?

Yes, please :+1:

[skokvermon]

pull requests have been made for 3 repos some benchs like tb-axi-delayer are working under vivado. A lot of other benches are doing segfaults during elaboration.

https://github.com/pulp-platform/axi/pull/232