andreaskurth
commented
2 years ago Thanks for your question, @fatihgulakar. How did you parametrize axi_sim_mem? In particular, what are the values of ApplDelay and AcqDelay? If they are both 0, the parallel processes in axi_sim_mem may be scheduled in the wrong order. Can you try setting ApplDelay to 1/4 of the clock period and AcqDelay to 3/4 of the clock period (might require increasing time precision in the simulator)?
If that helps, we should extend axi_sim_mem with assertions and its specification with the parameter constraints.
If that does not help, can you please paste a waveform where all signals of the AW, W, and B channels as well as the W monitor are visible?
Hi,
I am designing a multi-master system using Pulp's Axi modules. In the system, N identical masters are connected to a slave through the axi_mux module. For testing, I put axi_sim_mem as a slave. A Block diagram of the system can be seen below,
When a master wants to write, it raises aw_valid & w_valid in the same cycle. W handshake occurs a couple of cycles after the AW handshake. While W handshake has not occurred yet, another AW is sent by another master. This is where I am having a problem. Since a second address is sent before data of the first transaction is received, axi_sim_mem writes the wrong data to the address. Let me show a waveform to be more clear.
You can see that handshakes AW0 and AW1 occur first. Then W0 and W1 handshakes take place. But looking at the mon_w signals, I see it writes first data to both addresses. Also, it's better to know that there is no burst in my system. So I assigned len=0, burst=BURST_INCR, and size=$clog(strobe_width) for the inputs of axi_sim_mem.
Is there a problem with the memory model or my system? I am relatively new to AXI protocol, I might be missing something.
Thank you