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pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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axi_pkg: keep hardcoded value in typedef for vivado ip packager #293

Closed CyrilKoe closed 1 year ago

CyrilKoe commented 1 year ago

[ From issue https://github.com/pulp-platform/axi/issues/292 ]

Since commit fe4e020 the typedefaxi_pkg::burst_t now relies on a Verilog parameter BurstWidth. https://github.com/pulp-platform/axi/blob/fd60be8b51a4fa7476856be162ce3334474592ba/src/axi_pkg.sv#L46 In Occamy emulation we use these typedefs at the ports of a custom packaged Vivado IP.

But Vivado requires that "the IP ports are contained within the port description of the HDL file" (c.f. doc page 14). So custom Vivado IPs can't use axi_pkg::burst_t at their top anymore (similar issue on this support thread)

We could maybe define the typdef with a numerical value and then the parameter based on the $size of this typedef. See proposition in https://github.com/pulp-platform/axi/commit/d2f98d691594c1a8dd1af5bedd5d37d965027535