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pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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axi_to_mem_interleaved: Add interface version #304

Closed bluewww closed 1 year ago

bluewww commented 1 year ago

Adds a module with an SystemVerilog interface analogous to the one in axi_to_mem_banked.