Open omeag opened 3 months ago
I encountered an error while compiling the CDC module. I tried compiling and simulating the CDC module using VCS, but I keep getting this error. Is it possible that I missed something? And here is my filelist.
`+incdir+../include/axi/ +incdir+../common_cells/ +incdir+../scripts/ +incdir+../test/ +incdir+../src/ +incdir+../common_cells-master/src/ +incdir+../common_cells-master/include/ +incdir+../common_verification-master/src/ ../common_cells-master/src/cf_math_pkg.sv ../common_cells-master/src/gray_to_binary.sv ../common_cells-master/src/binary_to_gray.sv
../common_cells-master/src/spill_register_flushable.sv ../common_cells-master/src/spill_register.sv
../common_cells-master/src/cdc_fifo_gray.sv ../include/axi/assign.svh ../include/axi/port.svh ../include/axi/typedef.svh ../src/axi_pkg.sv // Level 1 ../src/axi_intf.sv // Level 2 ../src/axi_atop_filter.sv ../src/axi_burst_splitter.sv ../src/axi_bus_compare.sv ../src/axi_cdc_dst.sv ../src/axi_cdc_src.sv ../src/axi_cut.sv ../src/axi_delayer.sv ../src/axi_demux_simple.sv ../src/axi_dw_downsizer.sv ../src/axi_dw_upsizer.sv ../src/axi_fifo.sv ../src/axi_id_remap.sv // Level 3 ../src/axi_cdc.sv ../src/axi_demux.sv ../src/axi_err_slv.sv ../src/axi_dw_converter.sv ../src/axi_from_mem.sv ../src/axi_id_serialize.sv ../src/axi_lfsr.sv ../src/axi_multicut.sv ../src/axi_to_axi_lite.sv ../src/axi_to_mem.sv
// Level 4 ../src/axi_iw_converter.sv ../src/axi_lite_xbar.sv ../src/axi_xbar.sv ../src/axi_to_mem_banked.sv ../src/axi_to_mem_interleaved.sv ../src/axi_to_mem_split.sv
// Level 5 ../src/axi_xp.sv
// files: ../test/axi_synth_bench.sv
../common_verification-master/src/clk_rst_gen.sv ../common_verification-master/src/rand_id_queue.sv ../common_verification-master/src/rand_verif_pkg.sv // files: ../src/axi_chan_compare.sv ../src/axi_dumper.sv ../src/axi_sim_mem.sv ../src/axi_test.sv ../test/tb_axi_cdc.sv`
I encountered an error while compiling the CDC module. I tried compiling and simulating the CDC module using VCS, but I keep getting this error. Is it possible that I missed something?
And here is my filelist.
`+incdir+../include/axi/ +incdir+../common_cells/ +incdir+../scripts/ +incdir+../test/ +incdir+../src/ +incdir+../common_cells-master/src/ +incdir+../common_cells-master/include/ +incdir+../common_verification-master/src/ ../common_cells-master/src/cf_math_pkg.sv ../common_cells-master/src/gray_to_binary.sv ../common_cells-master/src/binary_to_gray.sv
../common_cells-master/src/spill_register_flushable.sv ../common_cells-master/src/spill_register.sv
../common_cells-master/src/cdc_fifo_gray.sv ../include/axi/assign.svh ../include/axi/port.svh ../include/axi/typedef.svh ../src/axi_pkg.sv // Level 1 ../src/axi_intf.sv // Level 2 ../src/axi_atop_filter.sv ../src/axi_burst_splitter.sv ../src/axi_bus_compare.sv ../src/axi_cdc_dst.sv ../src/axi_cdc_src.sv ../src/axi_cut.sv ../src/axi_delayer.sv ../src/axi_demux_simple.sv ../src/axi_dw_downsizer.sv ../src/axi_dw_upsizer.sv ../src/axi_fifo.sv ../src/axi_id_remap.sv // Level 3 ../src/axi_cdc.sv ../src/axi_demux.sv ../src/axi_err_slv.sv ../src/axi_dw_converter.sv ../src/axi_from_mem.sv ../src/axi_id_serialize.sv ../src/axi_lfsr.sv ../src/axi_multicut.sv ../src/axi_to_axi_lite.sv ../src/axi_to_mem.sv
// Level 4 ../src/axi_iw_converter.sv ../src/axi_lite_xbar.sv ../src/axi_xbar.sv ../src/axi_to_mem_banked.sv ../src/axi_to_mem_interleaved.sv ../src/axi_to_mem_split.sv
// Level 5 ../src/axi_xp.sv
// files: ../test/axi_synth_bench.sv
../common_verification-master/src/clk_rst_gen.sv ../common_verification-master/src/rand_id_queue.sv ../common_verification-master/src/rand_verif_pkg.sv // files: ../src/axi_chan_compare.sv ../src/axi_dumper.sv ../src/axi_sim_mem.sv ../src/axi_test.sv ../test/tb_axi_cdc.sv`