Ara integration in Cheshire

[mp-17]

Add bare-metal Ara to Cheshire.

1. Add Ara dependency to Bender and bump CVA6.
2. Integrate Ara in cheshire_soc. The current configuration can host a 2-lane Ara without performance degradations.
3. Ara can be enabled or disabled with the corresponding configuration switch with a parameter. Two parameters configure the Ara instance (AraNrLanes to determine the number of vector lanes and VLEN to determine the bit width of a single vector register).
4. The FPGA flow implements Cheshire without Ara.

[MarekPikula]

Hi, I noticed that there are multiple Ara/Cheshire/MMU-related branches. I wanted to evaluate Ara with Linux, but for that to work, I suppose that it requires proper MMU support. Since Cheshire is supposed to run Linux, I wonder if this PR has Ara MMU support. I noticed that in Bender config, it refers to branches that don't include MMU patches from the mp/chs-ara branch.

Could you let me know if there is any working setup to make Ara work with Linux (with MMU support)? I can see that there are multiple branches (i.e., mp/chs-ara, rebase/mp/chs-ara, and the original @MaistoV fork), but it's not clear to me which of these is the most "current". Did you test it in simulation or in FPGA?

[mp-17]

Hello @MarekPikula,

We are internally working on a version of Ara that supports Linux on FPGA, which we plan to release in the next months gradually. The version that can now boot Linux is a bit messy and needs clean-up. Nevertheless, if you are interested and not afraid of the mess, there is something on GitHub as well: 1) Ara: https://github.com/mp-17/ara/tree/mp/chs-ara 2) CVA6: https://github.com/mp-17/cva6/commits/ara_cheshire 3) Cheshire: https://github.com/mp-17/cheshire_fork/tree/mp/chs-ara 4) SDK: https://github.com/MaistoV/cva6-sdk_fork/tree/cheshire

As a note: this is not what you see in this PR.

[MarekPikula]

Nice, thank you for the pointers to the right places. I tested it in FireSim on an AWS F1 FPGA, and it seems to be working fine. I haven't run any extensive tests or benchmarks yet, only some small testing algorithms I had at hand, but man, it is exciting.

[krabo0om]

Hi, @mp-17 thanks for the effort integrating ARA! How close is the current PR to be merged? Can we use this PR as-is on an FPGA with Linux?

[mp-17]

Hello @krabo0om,

I will soon rework this PR and write down how to use Ara on FPGA since we have reached a sufficiently stable version.

[MarekPikula]

Hi @mp-17, today I was trying to update my FireSim setup with the updated Ara (from the master branch) but stumbled upon the following synthesis error from Vivado:

[Synth 8-2105] illegal cast operation

For the following lines:

• https://github.com/pulp-platform/ara/blob/main/hardware/src/ara_dispatcher.sv#L809
• https://github.com/pulp-platform/ara/blob/main/hardware/src/ara_dispatcher.sv#L1015
• https://github.com/pulp-platform/ara/blob/main/hardware/src/ara_dispatcher.sv#L1667
• https://github.com/pulp-platform/ara/blob/main/hardware/src/ara_dispatcher.sv#L2337

If I remove the vlen_t'(...) cast, it gets synthesized without error (or warning), but I guess it's not really a good idea to do this without understanding what exactly causes the error. I have the new VLEN parameter initialized, so I'm at a loss as to what could cause this error. Did you encounter anything similar during your work towards FPGA compatibility?

[mp-17]

Hello @MarekPikula,

can the problem be linked to the fact that vlen_t depends on VLEN, which we now pass as a parameter? (it was from an included package before)

It's an ugly fix, but if you include VLEN from a package, the error should go away. Let me know.

[fulcrum34]

Hello @mp-17 Following the information in cheshire's mp/chs-ara, I was able to build cheshire-ara for genesys2 but seems its too big for it. I tried removing VGA, DMA, GPIO, VIO, ILA but without much gains. Below is the utilization report for Genesys2 with default config. Config NrLanes = 2 VLEN = 2048 (1024 per lane as in ara.mk)

Just want to ask, What am I missing here? Should disabling vector FPU be of any help?

[mp-17]

Hello @fulcrum34. We have only tried it on the VCU128, not yet on the Genesys2 board. You can try removing the FPUs and see if it fits.

[fulcrum34]

Hello @fulcrum34. We have only tried it on the VCU128, not yet on the Genesys2 board. You can try removing the FPUs and see if it fits.

Hi, Thanks! Yes I tried with FPUSupportNone and it fits easily but I have trouble getting it to boot linux or run baremetal. I have also worked a version with FPU but unsupported single Lane config (https://github.com/pulp-platform/ara/pull/75) to fit in. Another thing I noticed, 200MHz clock for dram_wrapper does'nt meet timing. I used 100Mhz to be safe but I believe we can go a bit higher.

I can connect using Openocd. See openocd.log and gdb.log but the uart terminal despite correct port and baud prints ????? The linux image does'nt boot nor does show up anything in the uart console. Not sure what am I missing... Once I reach a fix, I will release a PR. Hope it will help people out there with genesys2. Good day!!! 🙂