Peripherals Clock Gating

[Lore0599]

Peripherals Clock Gating

This PR adds an internal register to control Cheshire's peripherals clock gating.

ADDED - HW

• 32-bit register: Each bit controls one peripheral. Bits 6 to 0 drive the peripherals that can be inserted in Cheshire, i.e., UART, I2C, SPIH, VGA, USB, and SLINK. The 25 most significant bits of the register are reserved for future extensions.
• Each peripheral clock signal is generated by a _tc_clkgating

[Scheremo]

Mostly LGTM, I would not negate the clock gate inputs.