changing AXI datawidth is not available.

pulp-platform / cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

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changing AXI datawidth is not available. #156

Open SeongRyong0726 opened 2 days ago

SeongRyong0726 commented 2 days ago

Hi. I tried to change AXI data width (AxiDataWidth : from 64 to 128). However, this occurs several errors and it seems that cva6 cache system only allow 64bit data width. When I tried to fix them with AXI_downsizer module between CVA6 (64bit) and AXI-bar (128bit), it is blocked at booting stage.

I wonder Cheshire support that change via parameter, now. Thank you.!

paulsc96 commented 1 day ago

Hi,

Thanks for reporting this issue. In principle, AXI data widths of more than 64 bits should be supported, but we indeed did not test this extensively. I assume the issue lies with the fairly new data width parameterization support of CVA6, since all other AXI IPs are inherently designed to not be datawidth-specific.

We will look into this at the earliest convenience.