This PR modifies the cluster interface to use flattened AXI ports instead of the classic structured types defined in axi/typedef.sv.
The reason for this change is to address limitations introduced by the UPF standard, as supported by QuestaSim. Specifically, when isolation strategies are applied, UPF cannot handle ports with "complex" types, such as AXI ports, which are structured.
To resolve this issue, signals are flattened at the interface of each power domain and then internally reassigned to new structured signals, which can be propagated to downstream modules.
ADDED - HW
Flattened types
These types are defined for the flattened ports at the _chimeracluster interface and must not be overwritten:
narrow_in_resp_flat_t
narrow_out_req_flat_t
wide_out_req_flat_t
Flattened ports
These flattened ports have been introduced at the _chimeracluster interface and must be connected upstream:
narrow_in_resp_flat_o
narrow_out_req_flat_o
wide_out_req_flat_o
Structured internal signals
These internal structured signals are connected to the flattened ports upstream and to the downstream modules:
Structured to Flattened AXI Ports
This PR modifies the cluster interface to use flattened AXI ports instead of the classic structured types defined in
axi/typedef.sv
. The reason for this change is to address limitations introduced by the UPF standard, as supported by QuestaSim. Specifically, when isolation strategies are applied, UPF cannot handle ports with "complex" types, such as AXI ports, which are structured. To resolve this issue, signals are flattened at the interface of each power domain and then internally reassigned to new structured signals, which can be propagated to downstream modules.ADDED - HW
Flattened types
These types are defined for the flattened ports at the _chimeracluster interface and must not be overwritten:
Flattened ports
These flattened ports have been introduced at the _chimeracluster interface and must be connected upstream:
Structured internal signals
These internal structured signals are connected to the flattened ports upstream and to the downstream modules: