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pulp-platform / common_cells

Common SystemVerilog components
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update assertions for sv2v+yosys #164

Closed davideschiavone closed 1 year ago

davideschiavone commented 1 year ago

hey guys (@meggiman , @micprog , @SamuelRiedel ), I added a few ifdef SV2V to get rid of attributes, and ifdef SYNTHESIS around assertions.

Not sure whether SV2V is appropriate, I did not want to add ifdef ATTRIBUTES as it is really tool specific to SV2V, also I assume soon or later yosys will support systemverilog, thus sv2v won't be used again

davideschiavone commented 1 year ago

@niwis any news on this?

niwis commented 1 year ago

Hi @davideschiavone, sorry for the delay, this somehow got lost. I discussed this with @meggiman and we both agree that attributes are valid SystemVerilog syntax and we would like to avoid too many tool-specific ifdef guards in the source code. One proposal would be to use a sed-script to get rid of the attributes before passing the files to SV2V. e.g. the following command should achieve the same result:

sed -i 's/(\*[^\n]*\*)//g' src/*.sv

Regarding the assertions, I understand that some synthesis tools can handle/propagate these to some degree. If they are not compatible with yosys, perhaps it would make sense to introduce a dedicated YOSYS target similar to VERILATOR?

davideschiavone commented 1 year ago

suggestions accepted and made a new PR at #165