Clock divider configuration fails if divider value is 0

[fimtrey]

@meggiman I ran into another issue with the clock divider.

Following the description

// It is thus safe to statically tie the valid signal to logic high if // we can guarantee, that the div_i value remains stable long enough (upper // limit 2 output clock cycles).

I tied valid_i to 1 and connected div_i to a register which has a reset value 0.

That's when I noticed that after div_q = 0 is loaded, I'm not able to reconfigure the clock divider.

As far as I understood, it hangs in the WAIT_END_PERIOD state, because the following condition can never be satisfied. https://github.com/pulp-platform/common_cells/blob/f9528fa6e4d3080605c01074bdaf62dcb4aff7d2/src/clk_int_div.sv#L187

Thanks @niwis for pointing out that this is indeed independent of the configuration while the divider is turned off, it just popped up checking https://github.com/pulp-platform/common_cells/pull/171.