Closed micprog closed 1 year ago
With this change, mem_to_banks assumes at least 1 cycle latency to the memory bank, but cuts a possible timing loop (e.g., when in axi_to_mem).
With this change, mem_to_banks assumes at least 1 cycle latency to the memory bank, but cuts a possible timing loop (e.g., when in axi_to_mem).