pulp-platform / common_cells

Common SystemVerilog components
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a bug in lzc module? #181

Open allensted opened 1 year ago

allensted commented 1 year ago

in lzc module the comment says: /// If the input does not contain a zero, empty_o is asserted. Additionally cnt_o contains /// the maximum number of zeros - 1. if the WIDTH is power of 2, it works fine image

but if the WIDTH is not the power of 2,i.e WIDTH is 29 when in_i is empty, cnt_o is zero instead of 29-1 image

because in the rtl // if index is out of range if (unsigned'(k) * 2 > WIDTH - 1) begin : g_out_of_range assign sel_nodes[2 level - 1 + k] = 1'b0; assign index_nodes[2 level - 1 + k] = '0; // why not assign index_nodes[2 ** level - 1 + k] = WIDTH-1; end