Fix deadlock on div_i == 0 and avoid hold issues on ungated_output_clock

[meggiman]

Instead of storing div_i directly in the internal register div_q we normalize the value to be strictly larger than 0. This avoids the deadlock issue when preloading with 0. Furthermore this commit removes all combinational checks on the phase of ungated_output_clock to avoid hold issues in synthesis. This checks were required to wait until the clock enable signal has been latched by the ICG. Now, we instead use a dedicated flip-flop that tracks the current status of the output clock gate.

This fixes #172.

[fimtrey]

I tested in on a pynq-z2 FPGA and it works for my case and there're no hold issues anymore. Thank you @meggiman !