pulp-platform / common_cells

Common SystemVerilog components
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Lossy valid to stream #189

Closed meggiman closed 1 year ago

meggiman commented 1 year ago

This module helps to deal with sources that use a valid-only interface, that is they do not support backpressure i.e. cannot handle the case where the sink is not ready to accept a value. The module is implemented as FIFO with 2 elements. In contrast to a regular FIFO that stops accepting new transactions once the FIFO is full, this IP overwrites the last element entered into the FIFO. This means the input is always ready to accept new transactions, however, intermediate transactions might be overwritten by the latest one. On the output side, the module behaves like a regular ready-valid source i.e. once valid is asserted, data_o remains stable until the sink consumes them (by asserting ready_i).

The lossy_valid_to_stream module is helpful to connect configuration registers with IPs that could cause back pressure. In this case we might not care how long it takes for the config value to be sent to the IP but if we change the config value we want the latest value to be used regardless whether the previous value has already been forwarded or not.

meggiman commented 1 year ago

Yes that is correct. Since we are not allowed to revoke an already started transaction that is the only option we have if I am not mistaken.